AuSn Bump Services for Silicon Photonics (PIC)

Precision AuSn Solutions for Next-Generation Photonic Integrated Circuits (PICs)

The demand for high-performance silicon photonics is accelerating, and the need for reliable, high-precision interconnects has never been greater. In the rapidly evolving field of silicon photonics, Photonic Integrated Circuits (PICs) are at the forefront of enabling high-speed data transmission, advanced sensing, and efficient optical computing. At Nanosystems JP Inc., we specialize in providing advanced Gold-Tin (AuSn) bumping services, delivering the superior bonding, thermal conductivity, mechanical stability, and hermetic sealing essential for assembly and packaging in today's most demanding PIC applications.

We deliver wafer‑level AuSn using two complementary approaches thin‑film physical deposition with alternate Au/Sn layers and AuSn electroplating with tunable composition ensures you get the optimal solution for your specific application that meets the stringent requirements of modern photonics achieving robust and high-performance connections in these advanced devices.

Our Advanced AuSn Bump Fabrication Services

Wafer Sizes Supported: 4-inch, 6-inch, 8-inch, and 12-inch wafers, accommodating a wide range of production scales from prototyping to high-volume manufacturing.

We also support wafers with cavity.

We offer flexible and customizable AuSn bump solutions through two primary methods

1. Thin Film Au/Sn Alternative Multi-Layer‑Layer Physical Vapor Deposition (PVD)

• Process Overview: This is our premier solution for applications demanding the highest level of precision and uniformity. Utilizing state-of-the-art PVD technology, we deposit AuSn bumps via multiple alternating layers of gold (Au) and tin (Sn)stacked to the target stoichiometry; reflow forms Au–Sn intermetallics. We achieve exceptional control over the final solder alloy.

• Unmatched Uniformity and adhesion: Ensures excellent adhesion and consistent bump height and uniformity & composition across the entire wafer.

• High Purity: Creates a clean, void-free interface ideal for fluxless, high-reliability bonding.

• Fine Pitch Capability: Perfectly suited for complex devices with high-density interconnects.

• Precise Composition: Delivers the exact eutectic 80/20 AuSn composition critical for a low-stress, robust bond. controlled eutectic formation for optimal soldering performance.

• Customizable layer thickness and composition: Eutectic Au:Sn 80:20, 75:25, 70:30 and other custom compositions upon request to match your specific thermal and electrical needs.

2. AuSn Electroplating

• Process Overview: We provide electroplating services for AuSn bumps at various compositions (e.g., 80/20 Au/Sn or custom ratios), allowing for flexible alloy tuning based on your application requirements.

• For applications requiring thicker solder layers or specific alloy compositions, our advanced electroplating process offers excellent flexibility and cost-effectiveness.

• Compositional Flexibility: We can precisely co-deposit Au and Sn to achieve the target alloy composition directly, supporting eutectic and off-eutectic compositions.

• High-Volume Scalability: An efficient process designed for large-scale production runs, with excellent uniformity and scalability.

• Versatile Applications: Ideal for a wide range of components, from laser diodes to RF devices, including array bumping and packages that benefit from composition tuning.

• Cost-Effective: For larger bump sizes and volumes.

• Suitable for Specific Requirements: For applications requiring specific melting points or mechanical properties.

Best For: Higher bump heights/volumes and scenarios needing precise reflow profiles.

Technical Specifications at a Glance

Complete Interconnect Solutions: UBM, RDL & Finishes

A reliable bump requires a perfect foundation. We provide the complete interconnect solution by managing the critical routing and surfaces on both the chip and the substrate.

• Under Bump Metallurgy (UBM): We deposit robust, multi-layer UBM stacks (e.g., Ti/Ni/Au, Ti/Pt/Au) to ensure superior adhesion, diffusion barrier performance, and a highly solderable surface on the chip's contact pads.

• Redistribution Layer (RDL): We fabricate high-precision Redistribution Layers (RDL) to reroute electrical connections across the wafer, enabling modern, high-density packaging designs. [Learn more about our RDL fabrication services here].

• Final Pad Finishes: We also offer advanced surface finishes for your substrate, including high-reliability ENIGand ENEPIG, to guarantee a pristine, oxidation-free surface ready for bonding.

Designed for Silicon Photonics

• PIC Materials: Silicon, SiN, InP/Si hybrid, LiNbO₃ modulators, and more

• Use Cases: Laser/photodiode attach, TIA/driver co-packaging, flip-chip PIC-to-ASIC interconnects, and hermetic subassemblies

• Fluxless Reflow Readiness: Ideal for sensitive optical surfaces and low-outgassing builds

Applications in Silicon Photonics

AuSn bumps from Nanosystems JP Inc. are ideally suited for:

• Flip-chip bonding in PIC assemblies

• Optical transceiver modules

• Laser diode integration

• High-speed interconnects for 5G and beyond

• Hybrid laser attach to Si/SiN PICs (butt-coupled or grating-coupled)

• Detector and modulator attach with controlled standoff

• Flip-chip PIC-to-ASIC micro-bumping for co-packaged optics

• Hermetic subassemblies requiring stable, low-void joints