TSV Reveal &
Post-Processing
TSV reveal is one of the highest-risk sequences in advanced packaging, thinning an already-processed wafer to within micrometers of buried copper vias. Our complete reveal flow uses temporary carrier bonding for mechanical safety, controlled plasma etch for precise Cu tip exposure, SiN/SiO₂ passivation, CMP, and continues directly to RDL, UBM, and C4 bumping, all in one project, managed end to end by a dedicated project manager.
steps
thickness after grind
control
etch control
Exposing buried copper vias
from the wafer backside
After TSV fabrication, the copper vias are fully enclosed inside the silicon wafer. TSV reveal is the sequence of steps that thins the wafer from the backside and exposes the Cu tips, creating the backside electrical contacts needed for 3D-IC stacking and flip-chip bumping.
Detailed process flow
Each step has tight constraints on temperature, selectivity, and planarity, and the order matters: a skipped backside dielectric step causes RDL shorts, a missed reveal CMP leaves the TSVs capped, and aggressive grinding into the copper causes smearing and wheel contamination.
Six steps from full-thickness TSV wafer
to bumped, assembly-ready die
Each step builds on the previous, and each requires thin-wafer-adapted process conditions that differ from standard wafer processing.
Temporary Bonding to Carrier Wafer
The device wafer, active surface facing down, is bonded to a rigid glass or silicon carrier wafer using a releasable temporary adhesive film or spin-coated adhesive layer. The carrier provides the mechanical support that makes all subsequent thinning and processing steps safe. Adhesive material is selected based on the maximum temperature the subsequent PECVD deposition will reach, the debond method (thermal, UV, or mechanical), and the solvent compatibility with the device wafer's surface materials. Bond quality is inspected by acoustic microscopy or optical imaging before the stack enters the grinder. The carrier remains bonded throughout grinding, reveal etch, passivation deposition, and CMP, it is only released after the backside is fully processed.
Backside Grinding
The bonded stack is loaded into the backside grinder, the carrier wafer provides rigid support during aggressive grinding. A coarse diamond wheel removes the bulk of the silicon, approaching the TSV tips from the backside. The grinding stops several micrometers above the Cu tip depth, leaving a thin silicon skin that protects the vias during the grinding step (Cu is softer than Si and would smear under grinding conditions). Target wafer thickness is typically in the range of 50 to 100 µm depending on TSV depth and via pitch, controlled to ±2 µm within-wafer uniformity. After coarse grinding, a fine-polish or stress-relief CMP step removes the sub-surface damage layer created by the grinding wheel, this is critical because the damage layer would create fracture initiation points if left in the thinned wafer.
Silicon Dry Etch Reveal
A controlled SF₆-based plasma etch recesses the remaining thin silicon skin around the TSVs, selective to the oxide liner that still caps each via, so the Cu is not exposed at this step. This is the most precision-demanding step in the reveal flow. The etch must: (a) remove Si selectively to the liner oxide, (b) recess uniformly across all vias on the wafer so the lined via tips stand proud by a controlled 1 to 2 µm, and (c) leave a tip profile that the passivation can cover conformally. Optical emission spectroscopy (OES) monitors the etch and the recess depth is confirmed by profilometry across the wafer before passivation deposition.
SiN / SiO₂ Passivation Deposition
After the recess etch, the entire backside, exposed Si, via sidewalls, and the protruding lined via tips, must be electrically insulated and protected. PECVD SiN (silicon nitride) and/or SiO₂ layers are deposited conformally at low temperature (<300 °C, compatible with the temporary adhesive) over the entire backside surface. The passivation serves three functions: electrical isolation between adjacent vias and the Si substrate; mechanical protection of the delicate revealed structure; and copper oxidation prevention. The deposition must achieve conformal coverage around the protruding via tips without creating voids or shadow regions that would leave exposed Si between the tip and the passivation layer.
CMP, Expose Cu TSV Contacts
The PECVD passivation covers everything, including the capped tops of the vias. CMP removes the passivation and the liner cap from the via tops, exposing the Cu for the first time; the stop point is set from the measured passivation thickness and confirmed by post-CMP inspection of the exposed Cu tips. The surrounding passivation remains intact, providing the dielectric surface for RDL deposition. Post-CMP, the wafer surface presents clean Cu contact pads flush with the surrounding SiN/SiO₂ dielectric, the contacts for subsequent RDL metallization. Surface roughness, Cu recess depth, and passivation thickness are measured and reported. The carrier wafer remains bonded throughout this step.
RDL → UBM → C4 Bumping
With clean Cu TSV contacts on the backside, the wafer proceeds to redistribution layer (RDL) fabrication, within the same project. RDL lithography and Cu electroplating or polymer passivation routes the TSV contacts from via pitch to bump pitch. Under Bump Metallization (UBM), ENIG (electroless Ni immersion Au) or ENEPIG (electroless Ni electroless Pd immersion Au), is then deposited on the RDL pads to provide solder wetting, adhesion, and diffusion barrier in the final bump interface. C4 (Controlled Collapse Chip Connection) SnAg solder balls are then formed by electroplating through a photoresist mask, self-aligning during reflow. The carrier wafer is debonded only after the last of these steps, when the RDL and passivation layers are complete and the wafer is transferred to its frame or shipping carrier.
TSV reveal process parameters
Typical values for the complete reveal and backside flow. Figures are targets, confirmed at engineering review for each program.
| Parameter | Specification | Notes |
|---|---|---|
| Carrier wafer material | Glass or silicon | Glass enables UV debond; Si suits thermal or mechanical debond |
| Adhesive type | Thermal, UV or mechanical release | Selected per device material constraints |
| Adhesive temperature rating | Up to 300 °C | Must exceed the PECVD deposition temperature |
| Grinding target thickness | 50 to 200 µm (typical) | Set by TSV depth and via pitch |
| Grinding uniformity | ±2 µm within wafer | Coarse-to-fine grinding sequence |
| Post-grind stress relief | CMP or dry polish | Removes grinding-induced subsurface damage |
| Reveal etch chemistry | SF₆ plasma (Si selective) | High Si:Cu selectivity |
| Recess etch control | Monitored by optical emission spectroscopy (OES) | Lined via tips left proud by 1 to 2 µm |
| Via tip protrusion | Measured by profilometry | Uniformity confirmed before passivation |
| Passivation material | PECVD SiN and/or SiO₂ | Conformal over the via tips |
| Passivation temperature | Below 300 °C | Compatible with the temporary-bond adhesive |
| CMP endpoint method | Stop on thickness target, inspect after CMP | Exposed Cu tips confirmed by inspection |
| Post-CMP surface | Cu contacts coplanar with the dielectric | Ra and recess depth measured and reported |
| RDL options | Polymer passivation or Cu damascene | BCB, PBO, PI or single/dual damascene |
| UBM options | ENIG or ENEPIG | Solder wettability plus diffusion barrier |
| Bumping | C4 SnAg electroplating | Self-aligned reflow |
| Carrier debond timing | After C4 bumping | Debond once backside processing is complete |
| Wafer size | 2 to 12 inch (300 mm) | All standard diameters |
Why This Is the Highest-Risk Step
At 50 µm thickness, a silicon wafer is fragile and must stay on a carrier through reveal. Every subsequent process step, PECVD deposition, CMP, lithography, must be adapted for thin-wafer conditions with a carrier substrate providing rigid support throughout. One missed step without carrier support and the wafer is lost.
Precision of the Reveal Etch
After backgrinding, a thin silicon skin remains around the lined via tips. The plasma recess etch must remove this skin selectively to the liner oxide, leaving the capped tips proud by a controlled 1 to 2 µm. Too little etch leaves vias buried; too much over-recesses the field and creates tip non-uniformity that compromises passivation coverage and later bonding. Optical emission spectroscopy monitors the etch in real time, and the recess depth is confirmed by profilometry.
The Backend Flow That Follows
After reveal and CMP, the wafer has clean Cu contacts on its backside, but this is not yet a finished product. RDL fabrication reroutes the via contacts to the required bump pitch; UBM provides the solder-wettable surface; C4 bumping forms the final flip-chip interconnects. All three steps continue in the same project.
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