Wafer Bonding: Eight Techniques
At Nanosystems JP Inc., we offer a comprehensive wafer bonding capability covering eight bonding techniques. From room-temperature hybrid bonding with ±1 µm Cu-Cu alignment, to eutectic hermetic seals from about 280 °C (AuSn) to about 424 °C (Al-Ge), to ultra-high vacuum SAB for LiNbO₃-Si heterogeneous integration. Chips to 12-inch wafers. C-SAM inspection per the agreed plan.
alignment accuracy
AuSn to Al-Ge
chips also accepted
Every bonding method -
a single project with one point of contact
Many foundries offer two or three bonding methods. Nanosystems JP Inc. offers eight, from high-precision hybrid bonding for 3D-IC to hermetic anodic bonding for MEMS packaging. Your device may need more than one technique; we coordinate the full bonding sequence.
Five bonding methods using
an intermediate material
These methods use a deposited or applied intermediate layer, metal, eutectic alloy, glass, or polymer, to create the bond. The intermediate layer determines bonding temperature, mechanical strength, hermeticity, and electrical conductivity.
Hybrid Bonding
The leading technique for face-to-face 3D-IC stacking. Combines direct dielectric fusion bonding (SiO₂-to-SiO₂) and Cu-Cu metal diffusion bonding in one integrated process. Both surfaces are CMP-planarized to <0.5 nm Ra, plasma-activated, pre-bonded at room temperature under atmospheric pressure (dielectric layers bond via van der Waals), then annealed at 100 to 300 °C to drive Cu diffusion and form a solid Cu-Cu joint. Result: electrical connection and hermetic dielectric bond in a single step with ±1 µm die-to-wafer alignment accuracy.
Metal Diffusion Bonding
Also known as thermocompression bonding. Two metal surfaces, Al-Al, Cu-Cu, or Au-Au, are brought together under heat and mechanical compression. Metal atoms diffuse across the interface, creating a metallurgical joint that is both mechanically strong and electrically conductive in one step. No intermediate solder layer is required. The joint quality is verified by cross-section metallographic analysis. Used in hermetic MEMS packaging, optical module assembly, and 3D-IC bonding where solder reflow would introduce too much movement.
Eutectic Bonding
An intermediate eutectic alloy layer melts at a temperature lower than either constituent metal alone, enabling hermetic bonding at a lower temperature than the constituent metals; the profile for your stack is confirmed at engineering review. Available eutectic systems: AuSn (melts at ~278 °C, 80Au:20Sn), AuGe (~361 °C), AuSi (~363 °C), AlGe (~424 °C). The eutectic alloy is deposited by sputtering with adhesion layers (Ti or Cr) and diffusion barriers (Ni or Pt). Pre-treatment removes surface oxide by wet or dry etching before bonding. Produces hermetic seals (hermeticity confirmed by leak test) for MEMS gyroscopes, accelerometers, and RF MEMS switches.
Glass Frit Bonding
A specially formulated glass paste (glass frit) is applied to one wafer surface by spin coating or screen printing, then heated to compact the frit into a dense glass layer, and finally bonded under thermo-compression at approximately 400 °C. The glass frit composition is engineered to match the coefficient of thermal expansion (CTE) of the bonded materials, critical for preventing crack initiation during temperature cycling. Bonds glass-to-metal, glass-to-ceramic, and glass-to-silicon. Primary application: hermetic MEMS package lids on pressure sensors, gyroscopes, and MEMS resonators.
Adhesive Bonding
Polymer adhesive bonding with selected low-temperature adhesives, thermally or UV-curable; cure and bonding temperatures are grade-specific (some epoxy and UV-curable grades cure well below 200 °C, while standard BCB and polyimide grades cure at roughly 250 °C or higher). Available adhesives: polyimide (PI), epoxy, and BCB (benzocyclobutene). Permanent bonding for the final device, or temporary bonding using releasable adhesive films for carrier wafer attachment during thinning operations. BCB offers particularly low dielectric constant and excellent planarization for applications where the polymer layer must also serve as an interlayer dielectric. A flexible, low-cost bonding technique; compatibility with completed CMOS wafers is reviewed against the device's full thermal budget.
Direct bonding, no adhesive,
no solder, no frit
Three techniques bond wafer surfaces directly, no intermediate material. Fusion bonding, surface-activated bonding (SAB), and anodic bonding each use different physics to achieve permanent bonds at the wafer level.
Fusion Bonding (Direct Bonding)
Hydrophilic silicon wafer surfaces are bonded at room temperature by van der Waals forces after rigorous CMP cleaning and surface activation. The pre-bond interface contains water molecules and Si-OH groups that later condense during annealing (100 to 300 °C) to form permanent covalent Si-O-Si bonds across the interface, with bond energy approaching bulk silicon after anneal; the value depends on anneal temperature. Plasma-activated fusion bonding uses O₂ or N₂ plasma to increase surface hydroxyl density and reduce the required annealing temperature. Pre-bonding surface roughness must be <0.5 nm Ra, confirmed by AFM before bonding. Bubble-free bond verified by IR transmission imaging.
Surface Activated Bonding (SAB)
In ultra-high vacuum (UHV), the wafer surface is bombarded by a Fast Atomic Beam (FAB), removing the native oxide and contamination layer without heating. The activated surface bonds to another activated surface at room temperature with covalent bond strength, no annealing required. This enables bonding of dissimilar materials that would delaminate during annealing due to CTE mismatch: LiNbO₃ wafer to Si (for optical modulators and SAW-MEMS hybrid filters), metals to ceramics, and compound semiconductors to Si. Maximum applied load: 100kN. Available for wafers and individual chips.
Anodic Bonding
An electric field is applied across a borosilicate glass (sodium-containing) wafer bonded against silicon or metal at 250 to 450 °C. The electric field drives Na⁺ ions away from the glass-silicon interface, creating a depletion region. Oxygen ions at the interface then migrate into the silicon, forming permanent Si-O bonds, a hermetic seal (hermeticity confirmed by leak test) without any intermediate material. The bonded structure can be glass-Si, glass-Si-glass (triple stack), or glass-metal. Alignment by IR-transparent imaging through the glass. Chip-scale to full 12-inch wafers. Primary applications: MEMS pressure sensors, gyroscopes, microfluidic chips, and photonics hermetic packaging.
Scanning Acoustic Microscopy
on bonded wafers
A bond that looks good on the outside may contain internal voids, delaminations, and unbonded regions invisible to optical inspection. C-SAM (scanning acoustic microscopy) maps the bond interface acoustically before the wafer proceeds to subsequent processing, on the sampling agreed in the inspection plan.
Every bonded wafer pair is scanned by C-SAM before proceeding. The acoustic map shows void density, unbonded edge regions, and delamination zones, quantified as a bond yield percentage. This data is included in the process report delivered to the customer.
| Technique | Temperature | Hermeticity | Electrical | Alignment | Primary Application |
|---|---|---|---|---|---|
| Hybrid Bonding | 100 to 300 °C | Yes (dielectric) | Yes (Cu-Cu) | ±1 µm | 3D-IC HBM stacking, logic-on-memory |
| Metal Diffusion (Al-Al) | 350 to 450 °C | Partial | Yes | ±2 µm | MEMS hermetic lid, thermocompression |
| Metal Diffusion (Cu-Cu) | 250 to 400 °C | Partial | Yes | ±2 µm | 3D-IC via bonding |
| Metal Diffusion (Au-Au) | 200 to 350 °C | Partial | Yes | ±2 µm | RF MEMS, optical module die attach |
| Eutectic, AuSn | ~280 °C | Hermetic-capable (leak test confirms) | Yes | ±3 µm | RF MEMS, VCSEL packaging, SiPho |
| Eutectic, AuGe | ~361 °C | Hermetic-capable (leak test confirms) | Yes | ±3 µm | Infrared detector packaging |
| Eutectic, Al-Ge | ~424 °C | Hermetic-capable (leak test confirms) | Yes | ±3 µm | MEMS sensor hermetic enclosure |
| Glass Frit | ~400 °C | Hermetic-capable (leak test confirms) | No | ±5 µm | MEMS package lids, pressure sensors |
| Adhesive, PI / BCB | <250 °C | No | No | ±3 µm | Temporary carrier, flexible integration |
| Fusion Bonding | RT → 100 to 300 °C | Yes | No | ±1 µm | SOI, pre-TSV bonding, MEMS cap |
| SAB (Ultra-high vacuum) | Room temp | Yes | No | ±2 µm | LiNbO₃-Si, dissimilar material bonding |
| Anodic Bonding | 250 to 450 °C | Hermetic-capable (leak test confirms) | No | IR align | MEMS sensors, microfluidics |
Wafer bonding across every
semiconductor market
3D-IC Memory Stacking (HBM)
Hybrid (Cu-Cu plus dielectric) bonding for memory-on-logic stacking evaluation, logic die bonded face-to-face to a DRAM layer at ±1 µm Cu-Cu precision. Production HBM generations use microbump or hybrid-bond interfaces; the interface for your stack is defined at engineering review.
Hermetic MEMS Packaging
Anodic and glass frit bonding for hermetically sealed MEMS gyroscopes, accelerometers, and pressure sensors. The hermetic cavity maintains vacuum or inert atmosphere, critical for long-term resonator Q-factor and sensor stability. Suited to automotive and aerospace reliability programs; qualification is run by the customer.
Silicon Photonics Integration
Fusion and adhesive bonding of III-V compound semiconductor laser dies (InP, GaAs) to silicon photonic waveguide chips. SAB for LiNbO₃ modulator substrate bonding to Si. Low-temperature techniques prevent thermal degradation of waveguide coupling efficiency.
RF MEMS & SAW/BAW Filters
Eutectic AuSn bonding for hermetic flip-chip packaging of RF MEMS switches and SAW/BAW resonator chips. The AuSn eutectic temperature is approximately 280 °C; the bonding profile and compatibility with LiNbO₃ or LiTaO₃ are reviewed for the specified stack. Used in 5G front-end modules.
Microfluidics & BioMEMS
Anodic bonding seals glass-Si-glass microfluidic chips for DNA sequencing flow cells, electrophoresis chips, and point-of-care diagnostic devices. PDMS adhesive bonding for lab-on-chip research devices. Glass-Si hybrid chips with TSV electrical feedthroughs.
Power Module Packaging
Thermocompression Au-Au die attach for SiC MOSFET and GaN transistor power modules requiring high-temperature operational stability. Glass frit bonding for ceramic-to-metal package sealing. Applied to automotive inverter modules and industrial power converters.
Image Sensors (BSI Stacking)
Fusion bonding of backside-illuminated (BSI) image sensor pixel wafer to CMOS readout wafer. Pre-bonding CMP achieves the surface flatness needed for large-area direct bonding. Critical for consumer camera, scientific, and surveillance imaging sensors.
Optical MEMS & LIDAR
Eutectic or adhesive bonding for optical MEMS devices, MEMS mirrors for LIDAR beam steering, tunable Fabry-Pérot filters, and micro-spectrometers. Low-outgassing adhesive bonding maintains vacuum in optically sensitive cavities.
SOI & Engineered Substrates
Fusion bonding of Si to oxidized Si handle wafer, the basis of Silicon-on-Insulator (SOI) substrate fabrication. Also: bonding of piezoelectric layers (LiNbO₃, LiTaO₃) to Si for RF filter engineered substrate manufacturing (RF-SOI and BAW filter templates).
Six ways to join wafers
Every stack on this page lands on one of these six interfaces; the drawings show what each joint actually is.
What makes our wafer bonding
capability different
All 8 techniques in one coordinated process flow
Hybrid, metal diffusion, eutectic, glass frit, adhesive, fusion, SAB, and anodic, the complete toolkit. Your device stack may need hybrid bonding for 3D-IC plus anodic bonding for the MEMS cap, both done in the same project.
Hybrid bonding for 3D-IC at prototype scale
±1 µm Cu-Cu + SiO₂ hybrid bonding available from 1-wafer prototypes, not only for high-volume production lots. Pre-bonding CMP to <0.5 nm Ra is integrated in the same project. Planarization is included in the same project.
SAB for LiNbO₃ heterogeneous integration
Ultra-high vacuum surface-activated bonding for LiNbO₃-on-Si, enabling next-generation optical modulator and RF filter substrates. Offered by only a limited number of services worldwide. The CTE mismatch between LiNbO₃ and Si makes this impossible with conventional fusion bonding.
CMP + bonding in the same project
Pre-bonding CMP to achieve <0.5 nm Ra surface roughness for fusion and hybrid bonding is managed within the same project. Surface degradation between CMP and bonding is one of the most common failure modes in fragmented process flows. Running CMP and bonding as one project eliminates that risk.
C-SAM inspection before the next step
Bonded wafers are scanned by scanning acoustic microscopy before proceeding, on the sampling agreed in the inspection plan. A bond yield map is provided to the customer. Voids detected before dicing, not discovered at final test after all subsequent processing has been completed on a defective wafer.
Chip-to-wafer and wafer-to-wafer
Bonding available from individual chips (chip-to-wafer hybrid bonding for known-good-die stacking) to full 12-inch wafer-to-wafer. Useful when two dies being bonded are fabricated on different wafer sizes, common in heterogeneous photonic integration.
Hermetic sealing for
MEMS and sensor packages
Several bonding techniques available at Nanosystems JP Inc. are used to form hermetic seals in device packaging, protecting sensitive MEMS structures from atmospheric exposure over the device lifetime. The appropriate technique depends on process temperature constraints, substrate materials, and the required degree of isolation.
Anodic Bonding: Glass to Silicon
A widely used route for MEMS hermetic encapsulation. A borosilicate (alkali-containing) glass cap wafer is bonded directly to a silicon device wafer at moderate temperature using an applied electric field; the bond forms at the glass-silicon interface without an intermediate layer, leaving the device cavity clean. Fused silica caps cannot be anodically bonded and use an intermediate-layer route reviewed per program. Suitable for inertial sensors, resonators, and pressure sensors.
Glass Frit Bonding
A patterned glass frit paste is screen-printed or dispensed as a seal ring on the cap wafer, then reflowed during bonding. The technique tolerates surface topography variations better than direct bonding and is compatible with pre-released MEMS structures. Fused silica cap wafers with TGV feedthroughs can be integrated into glass frit bonding flows.
Eutectic Bonding: AuSn & AuGe
Metal eutectic bonding (AuSn, AuGe) provides a robust hermetic seal at relatively low process temperatures. The approach is used for compound semiconductor device packages, optoelectronic components, and applications requiring a metal seal ring around the device cavity.
TGV Cap Integration
For devices requiring both hermetic sealing and electrical feedthroughs through the glass cap, we coordinate TGV formation in fused silica or borosilicate glass with subsequent wafer-level bonding. Fused silica caps offer the additional benefit of optical transparency (UV to IR), making them suitable for optical sensor packages where light must pass through the cap layer. The complete sequence, substrate supply, via drilling, and bonding, is managed under one project at Nanosystems JP Inc.
Cu-Cu hybrid bonding
for chiplet integration?
Hybrid bonding is one step in a complete AI & HPC interposer packaging flow, TSV, TGV, RDL, and bonding all managed as one project at Nanosystems JP Inc.
🧪 Pre-bond surface cleaning: SC1, RCA, and piranha wet chemical cleaning can be coordinated as a pre-bond preparation step, critical for direct bonding, fusion bonding, and anodic bonding where surface cleanliness directly affects bond strength and void density.
Cleaning services →Dedicated pages that start from this process
The full page for glass caps, microfluidic covers and triple stacks, including cavity and feedthrough options.
Caps made to your layout, delivered alone or bonded to your device wafer.
Start your project.
Initial response typically within one business day.
Share your process requirements, substrate, and production volume. A Nanosystems JP Inc. engineer will give an initial response typically within one business day. Full quote typically within 7-10 business days, subject to project complexity and NDA requirements.