Core Semiconductor Processes: Step 11

Wafer
Dicing Services

At Nanosystems JP Inc., we offer four dicing methods for every material, die shape, and substrate format. Stealth laser dicing, dry, no water, no dust and no front-side chipping on qualified materials, for silicon photonics PICs and fragile MEMS. Blade dicing for standard Si/glass 4 to 12 inch. Large-format glass to 500 × 600 mm. Diamond scribing for SiC/AlN/InP. Polygon dies (hexagon, octagon). Inspection, sorting, tray packing.

Have full specs ready? Submit a detailed Technical RFQ →

Standard blade Si/glass 4 to 12 inchLarge glass 300 × 400 / 500 × 600 mmStealth laser, dry, no dustDiamond scribing SiC/AlN/InPPolygon dies hex/octagonSiPho wafer dicingMetals Cu/SUS/AlInspection · Sorting · Tray pack
4
Dicing methods
500 × 600 mm
Max glass panel
Polygon
Hex & octagon dies
Dry process
Stealth, no water, chipping per criteria
Four Dicing Methods
Choose by material, die shape, and quality requirement

Each dicing method has distinct advantages for different substrate materials, die sizes, and cleanliness requirements. Our engineers recommend the optimal method based on your device.

Standard Blade Dicing, Silicon

Rotating diamond blade dicing for silicon wafers from 4 to 12 inches. The workhorse of MEMS and IC singulation for rectangular dies on standard circular substrates. Automatic wafer map reading enables die-level quality sorting, accepted and rejected dies identified before dicing begins. Kerf width controlled to ±2 µm for maximum die yield from expensive wafers. Cooling water spray prevents blade overheating and removes silicon swarf during cutting.

4 to 12 inch SiRectangular diesWafer map auto-read±2 µm kerf controlCooling water spray

Blade Dicing, Glass & Ceramic

Glass dicing for circular wafers (4 to 12 inch) and large rectangular panels up to 500 × 600 mm. Quartz, borosilicate, aluminosilicate, and alumina (Al₂O₃) diced with glass-specific blades at lower feed rates than silicon. Thick glass dicing available for glass interposer substrates and MEMS package lids. Large-format glass dicing (300 × 400 mm and 500 × 600 mm) for display substrates, biochip arrays, and panel-level packaging, a capability beyond the circular-wafer limit of standard dicing houses.

4 to 12 inch glass500 × 600 mm panelsQuartz · Alumina · BorosilicateGlass-specific bladesBiochip · Interposer · Display

Stealth Laser Dicing

A pulsed laser modifies a plane inside the silicon wafer along the dicing streets without breaking the surface or producing any debris. A subsequent tape expand step singulates the dies, completely dry, no water, no dicing debris, no blade contact. Stealth dicing is selected where optical waveguide facet quality must be preserved and fragile MEMS membranes protected from water and particle contamination; edge damage and facet roughness are qualified against the application. Enables polygon-shaped dies (hexagonal, octagonal) impossible with straight-blade dicing. No change in die size limitation, works from sub-millimeter dies to large multi-centimeter dies.

Dry, no waterNo dust or debrisLow chipping on qualified materialsPolygon dies (hex/oct)SiPho waveguide facets protected

Diamond Scribing

Mechanical scribing with a diamond tip along the dicing street followed by controlled cleaving, a standard singulation method for single-crystal compound semiconductors with cleavage planes that chip or crack under blade dicing contact. InP and GaAs have preferential crystallographic cleavage planes that guide the cleave, producing clean die edges; SiC and polycrystalline AlN ceramic are diced by blade or laser. Applied to InP photonic dies and GaAs MMIC chips where blade contact causes micro-cracking at the die edge that degrades electrical isolation and mechanical reliability.

SiC · AlN · InP · GaAsDiamond tip scribingControlled cleaveCrystallographic cleavage guidedNo micro-cracking
Stealth Laser Dicing
Why silicon photonics and MEMS customers choose stealth over blade
Conventional blade dicing floods the wafer with cooling water at high pressure, producing dicing debris (silicon swarf) that contaminates optical waveguide facets, MEMS cavities, and fragile membranes. For silicon photonic PICs, water and particles at the cleaved waveguide facet cause permanent coupling loss. For MEMS with fragile membranes, water surface tension during drying fractures the membrane. Stealth laser dicing modifies only the interior of the silicon, the surface never contacts water or blade.
Dry process, no water spray ever contacts the wafer surface
No dicing debris or silicon swarf generated
Minimal edge chipping on qualified materials, interior-only laser modification
Compatible with low-k dielectric device layers (fragile to mechanical stress)
Polygon dies: hexagonal, octagonal and custom software-defined outlines, confirmed per material and thickness
Full wafer processed without wet exposure at any step
MEMS fragile membranes, cantilevers, and bridges survive intact
Silicon photonics waveguide facets protected, coupling efficiency maintained
Stealth pattern defined by software, no tooling cost for new die shapes
Enables dicing of fully packaged wafer-level packages after molding
Additional Materials
Metal substrates, large glass, and more

Metal Substrate Dicing

Dicing of metal substrates and MEMS-on-metal devices, copper foil, stainless steel (SUS), and aluminum sheets. Requires specialist metal-cutting blades different from semiconductor dicing wheels. Applied to flexible circuit singulation, metal-substrate MEMS sensors, and thin-film devices on metal foil where conventional wafer dicing blades would deform the substrate rather than cut it cleanly.

Cu · SUS · AlMetal-specific bladesMEMS on metalFlexible circuit dicingMetal foil devices

Large-Format Glass Dicing

The most distinctive dicing capability we offer: 300 × 400 mm and 500 × 600 mm rectangular glass substrate dicing for applications that produce many chips per panel. Biochip arrays, display glass singulation, glass interposer panels, and microfluidic chip singulation all require panel-format dicing far beyond what 300 mm circular wafer dicing tools can process. Glass-specific cutting parameters prevent the micro-cracking and edge chipping that standard Si blade parameters cause in glass.

500 × 600 mm panels300 × 400 mm panelsBiochip arraysDisplay glass singulationGlass interposer dicing

Polygon-Shaped Dies

Hexagonal, octagonal, and other non-rectangular die shapes enabled by stealth laser dicing, the laser path is entirely software-defined, so any polygon shape is achievable without tooling. Used for circular optical elements (where a rectangular die wastes chip area), RF antenna chips (where die shape follows the antenna pattern), and die geometries optimized for non-rectangular device layouts or assembly into cylindrical packages.

Hexagon · OctagonPolygon dies by laser dicingSoftware-defined pathNo tooling costCircular optical elements
Post-Dicing Services
Inspection, sorting, and tray packing

Automated Optical Inspection

Post-dicing AOI scans every die for chipping at the kerf edge, surface particles, delamination, and cracks. Map-based sorting identifies and records the position of every defective die before any physical handling occurs. Electro-optical testing available for silicon photonics dies, coupling efficiency measured on-wafer before dicing as part of the known-good-die selection process.

AOI every dieKerf chip detectionMap-based sortingSiPho optical testPre-dicing EO test

Die Sorting & Known-Good-Die

Sorted die placement by quality grade, known good die (KGD), marginal, and reject, recorded against the wafer map. Dies picked from tape and placed into waffle packs or JEDEC trays according to wafer map coordinates. KGD selection enables downstream flip-chip and die bonding assembly to use only verified good dies, reducing assembly yield loss and avoiding costly post-assembly test of bad die.

KGD selectionWaffle packJEDEC trayMap-coordinate placementYield improvement at assembly

Tray Packing & Shipment

Singulated dies packed in JEDEC-standard and custom trays with anti-static and anti-humidity measures. Controlled humidity storage and nitrogen-purged sealed bags for compound semiconductor dies sensitive to surface oxidation (InP, GaAs). Traceable packing records, each tray labeled with wafer ID, die count, quality grade, and process data reference. Available for dies from sub-millimeter to large multi-centimeter sizes.

JEDEC traysAnti-static · Anti-humidityN₂ purge for InP/GaAsTraceable recordsAny die size
Dicing Specifications
All methods, substrate and capability overview
MethodSubstrate / SizeDie ShapeAccuracyKey Capability
Blade dicing, Si4 to 12 inch circularRectangular only±2 µm kerfStandard; water-cooled; fast throughput
Blade dicing, Glass4 to 12 inch; 300 × 400; 500 × 600 mmRectangular±5 µm kerfGlass-specific blade; panel format
Blade dicing, Thick glassAny; up to 500 × 600 mmRectangular-Interposer lids; MEMS packages
Stealth laser dicingSi wafers; any sizeRectangular (polygon dies via laser ablation)Sub-µmDry; no debris; SiPho; MEMS; polygon dies
Diamond scribingInP; GaAs; other single crystalsRectangular (cleave-guided)Crystal planesBrittle compound semi; no micro-cracking
Metal dicingCu; SUS; Al sheetsRectangular-Flexible circuits; metal MEMS
Large-format glass300 × 400 mm; 500 × 600 mmRectangular±5 µmPanel-scale capability
Applications
Dicing across every semiconductor market

Silicon Photonics PICs

Stealth laser dicing of SiPho wafers, preserving optical waveguide facet quality that water-based blade dicing permanently degrades. Clean facets directly after stealth dicing, no additional facet polishing required for many applications. Pre-dicing optical testing identifies KGD before singulation.

Stealth laser · Dry · Waveguide facets clean · SiPho PIC · KGD test

MEMS Sensors & Actuators

Stealth laser dicing of MEMS wafers with fragile membranes, cantilevers, and suspended structures, water from blade dicing causes membrane fracture by surface tension during drying. Polygon stealth dicing for MEMS with non-rectangular die geometries. Thick handle wafer dicing for MEMS packages.

Stealth laser · MEMS membranes safe · Polygon dies · IMU · Pressure sensor

SiC Power Chips

Blade or laser dicing of SiC wafers with recipes that limit micro-cracking at the die edges, which otherwise degrades high-voltage blocking capability. Applied to SiC MOSFETs, SBDs, and thyristors for EV inverters and industrial drives.

Diamond scribing · SiC cleavage · No micro-cracking · SiC MOSFET · EV inverter

Biochip & Glass Arrays

Large-format glass dicing (500 × 600 mm) of biochip arrays, singulating hundreds of biochip dies per panel run. Glass-specific dicing parameters prevent micro-cracking of glass channel structures. Quartz and fused silica dicing for DNA sequencing flow cells.

500 × 600 mm glass · Biochip array · Quartz · Fused silica · DNA flow cells

RF MMIC & mmWave Chips

Diamond scribing of GaAs and InP MMIC chips, avoiding the die-edge micro-cracking that blade dicing causes in III-V compound semiconductors. Clean die edges are critical for RF isolation between adjacent dies in module assembly. Gold-bottom dicing tape prevents metal contamination of compound semiconductor dies.

Diamond scribing · GaAs · InP · MMIC · RF isolation · mmWave

Consumer IC WLCSP

Standard blade dicing of thinned Si wafers (100 to 200 µm) carrying fan-in WLCSP-packaged ICs. Wafer map-guided sorting separates KGD from marginal and failed dies before tape mounting and tray packing for shipment to module assembly houses.

Blade dicing · Thin Si · WLCSP · KGD sort · JEDEC tray · Mobile/IoT

Display Glass Singulation

Large-format blade dicing of 500 × 600 mm display glass panels, singulating individual display substrates, sensor arrays, or biochip arrays from the panel. Panel-format dicing achieves dramatically lower cost-per-chip than wafer-format dicing for large substrate applications.

500 × 600 mm blade · Display glass · Panel singulation · Low cost-per-die

LSPR & Optical Microchips

Stealth laser dicing of LSPR biosensor chips and optical microchip arrays in non-rectangular geometries, hexagonal LSPR chip arrays, circular optical elements, and custom-footprint photonic dies. Software-defined stealth path enables any geometry without tooling cost.

Stealth laser · LSPR chips · Optical elements · Hexagonal dies · Custom polygon

AR/VR Optical Components

Stealth laser dicing of waveguide combiner chips and micro-optics for AR/VR headsets. Optical waveguide devices require the cleanest possible die edge, any chipping or particle near the coupler causes permanent coupling efficiency loss. Polygon stealth dicing for non-rectangular optical combiner footprints.

Stealth laser · Waveguide combiner · Clean edge · AR/VR · Polygon shape
Why Nanosystems JP Inc.
All four methods, a single project with one point of contact
01

Stealth dicing for SiPho and MEMS

Dry, chip-free stealth laser dicing for silicon photonics PICs and fragile MEMS, a method well suited to protecting optical waveguide facets and MEMS membranes, offered for production-scale SiPho dicing.

02

500 × 600 mm large-format glass

Panel-format glass dicing to 500 × 600 mm for display glass, biochip substrates, and glass interposers, far beyond the 300 mm circular wafer limit of standard dicing tools.

03

Polygon dies, custom outlines

Hexagonal, octagonal, and custom polygon dies by stealth laser, software-defined path, no tooling cost, no minimum lot size. New die outlines are confirmed per material and thickness and can be available from the next dicing run.

04

Compound semiconductor expertise

Diamond scribing for SiC, AlN, and InP, materials that chip under standard blade dicing. Crystallographic cleavage plane awareness prevents die-edge micro-cracking that degrades device performance.

05

Full backend service

Dicing, optical inspection, KGD sorting, and JEDEC tray packing. No separate dicing house and inspection house to coordinate. One delivery with complete die quality records.

06

Coordinated with backgrinding

Wafer thinning (CMP/grinding) and dicing are often sequential steps. Both handled in the same project, one schedule, one PM, one project.

Next in your process flow

Assembly: After dicing, dies move to flip-chip bonding or die attach; wafer bonding, where used, precedes dicing.

Flip-Chip Bonding →

Start your project.
Initial response typically within one business day.

Share your process requirements, substrate, and production volume. A Nanosystems JP Inc. engineer will give an initial response typically within one business day. Full quote typically within 7-10 business days, subject to project complexity and NDA requirements.

To speed up technical review, please include:
substrate type & size  ·  target process  ·  quantity  ·  timeline  ·  design files if available (not required for first review)

sales@nanosystemsjp.co.jp · +81-3-5288-5569 · NDA available

Choose the method

Stealth, laser or blade: which dicing route fits your wafer

Silicon to 300 mm, glass and fused silica, SiC and sapphire, thin and bumped wafers each favor a different cut. Start from the material.

Stealth and laser dicing →

Kerf-free stealth dicing for silicon and glass to 300 mm, laser grooving for metal and low-k streets, full laser dicing for brittle materials, SDBG for thin dies.

Blade dicing →

Diamond blade dicing for silicon, glass and ceramic to 500 × 600 mm panels, with kerf, chipping and street width agreed per lot.

Glass wafer dicing →

300 mm glass and fused silica wafers, windows and coupons cut by stealth, laser or blade routes chosen for the glass type.

Ready to discuss this process?
Initial engineering response: typically within one business day. NDA available.
Request a Quote →
Services & Industries
Capabilities Overview
Substrates
Substrate & WafersSi, SiC, GaN, glass, sapphire Fused Silica WafersQuartz · borosilicate · low CTE Glass ProcessingDrilling, etching, polishing PI Film & SUS Sensor FabRoll-to-roll · sensor patterning
Front-End
Mask FabricationGDS to chrome mask, DRC PhotolithographyE-beam 20 nm to 500 × 600 mm NanoimprintingUV & thermal NIL Thin Film DepositionPVD, CVD, ALD, MBE ALD CoatingConformal oxides, nitrides PECVD DielectricsSiO₂, SiN, SiON, a-Si TFT & BackplaneIGZO · Glass · Display Lift-OffMetal pattern · shadow mask ElectroplatingCu TSV fill, DPC, LIGA Electroforming & LIGANi shims, meshes, microstructures EtchingICP-RIE, DRIE >50:1 ICP-RIE EtchingSi, oxide, III-V, SiC, quartz MEMS FoundrySensors, actuators, microfluidics Microchannel CoolingEtched, bonded, heater test chips Thermal Test ChipsHeater dies, multi-zone, RTD Temperature SensorsPt/NiCr RTDs, thermocouples AnnealingN₂ / H₂ / vacuum / RTA Ion ImplantationB / P / As / Al / N implant CMP & GrindingCu CMP, 50 µm thinning Wafer ThinningTo 50 µm on carriers Backside MetallizationTi/Ni/Ag, Ti/Ni/Au, Ti/Cu Patterned Test WafersCustom CMP and process evaluation wafers Daisy-Chain Test DiesDummy dies, chains, bump options DicingBlade, stealth laser Stealth & Laser Dicing300 mm Si and glass, SDBG Wafer CleaningRCA, plasma, megasonic Cleaning ChemistryPiranha, SC-1, SC-2, RCA
Advanced Packaging
Wafer BondingHybrid, eutectic, fusion Anodic BondingGlass to silicon, cavities MEMS Cap WafersCavities, ports, seal lands, bonded TSV FabricationHigh AR, Cu fill InterposersSi and glass, TSV/TGV + RDL TSV RevealBackgrind → etch → CMP TGV FabricationThrough-glass via Glass TGV CouponsHole-only to routed prototypes RDL FabricationBCB / PBO / PI + damascene Packaging & AssemblyWire bond, flip-chip Flip-Chip BondingTC, reflow, AuSn, underfill 3D / 2.5D PackagingTSV + RDL + UBM + C4 AuSn BumpPVD lift-off, fluxless Laser SubmountsSi/AlN submounts, optical benches Indium BumpEvap lift-off · cryo/quantum UBM DepositionTi/Pt/Au · adhesion-barrier-Au Cu Pillar & SnAg BumpingPillars with SnAg caps, SnAg bumps Gold BumpEvap & plated · Au-Au TC AuGe / AuSi361/363 °C eutectic die attach High-Pb Bumps95Pb5Sn · hi-rel C4 SLID / TLPCu/Sn · Au/In · Ag/In Al-Ge Sealing424 °C · CMOS-friendly MEMS Ohmic ContactsGaAs · GaN · RTA + TLM SiC ProcessingThinning, films, contacts, dicing GaN & III-VGaN, GaAs, InP processing Cryo / UHV MetalAuSn · Ti/Pd/Au · rings Optical AccessWindows · meshes · holes Vapor CellsDRIE + bond · unfilled TFOI WafersQuartz-on-Si · LNOI Biochip & MicrofluidicsGlass 500 × 600 mm, NIL SiPho PackagingTSV · RDL · UBM · C4 for PIC Photonic DevicesSiN/SOI waveguides, gratings
Industries
AI & HPC PackagingCoWoS-style, 2.5D / 3D Silicon PhotonicsSOI · AuSn · TSV interposer AutomotiveMEMS sensors, SiC power Life SciencesLab-on-chip, biosensors All Industries → Request a Quote →