Ion
Implantation
Services
At Nanosystems JP Inc., we offer precision doping for SiC MOSFETs, GaN HEMTs, IGBTs, Ga₂O₃ power devices, and advanced MEMS. Implant energies from 0.1 keV to 100 MeV by machine class (plasma immersion below 1 keV; high energy on request), high-temperature implantation to 600 °C, 60+ dopant species, pre-implant simulations, and rapid thermal annealing to 1800 °C, all in one integrated flow.
temperature (SiC/GaN)
temperature
available
diameter
Precision implantation for
every device type
Our ion implantation service is built around power device requirements, particularly the demanding needs of SiC and GaN, where standard room-temperature implantation is insufficient for proper crystal activation.
High-Temperature Implantation
Elevated-temperature implantation is commonly used for high-dose SiC processes to limit implantation-induced lattice damage. The substrate temperature for SiC and GaN is selected according to ion species, dose, energy, and device requirements. We offer substrate heating to 600 °C, common for high-dose SiC MOSFET well implants; GaN HEMT isolation by N or F implant is usually run at room temperature.
Broad Dopant Selection
Over 60 dopant species available, covering all major n-type, p-type, and co-implant requirements across Si, SiC, GaN, GaAs, and Ga₂O₃. Rare species including Ca, Ba, La, Fe, Cr, and Sn available for advanced research and specialized device structures. Inquire for species not listed.
Versatile Wafer Compatibility
From small chips and 2-inch research samples to full 300 mm production wafers. Handles all standard semiconductor substrates including Si, SiC, GaN, GaAs, InP, Ga₂O₃, sapphire, and glass. Tilt angles from 0° to 60° for channeling suppression or controlled channeling implants.
Rapid Thermal Annealing (RTA)
Post-implant activation annealing to 1800 °C under Ar and N₂ atmospheres. Essential for activating Al, N, and B dopants in SiC, the highest-temperature step in power device fabrication.
Pre-Implant Simulations
SRIM/TRIM or TCAD simulations before processing, where appropriate. We model dopant distribution, peak concentration, straggle, and damage profiles to confirm your doping requirements are achievable before any wafers are processed.
Carbon Cap Processing
Carbon cap deposition before high-temperature annealing prevents silicon evaporation and step bunching from SiC surfaces. Essential for maintaining nm-scale surface roughness (low RMS) after 1400 °C+ anneals.
High-Energy & High-Concentration H
High-energy hydrogen implantation for layer separation (Smart Cut™-type processes), hydrogen-induced defect engineering, and high-concentration H for direct wafer bonding and SOI preparation. High-energy H⁺ isolation implant also used for VCSEL current aperture definition in photonic device fabrication.
Power Device Optimization
Process parameters optimized specifically for power semiconductor device fabrication, not standard CMOS profiles. Our engineers understand the unique electrical requirements of blocking junctions, channel implants, and ohmic contacts in SiC and GaN.
Post-Implant Characterization
Electrical and physical verification after implantation, available as part of the service flow. Four-point probe sheet resistance mapping on activated monitor wafers gives an electrical check of uniformity; beam dose is controlled by the implanter and depth profiles by SIMS on request. Particle inspection and surface contamination checks included. SIMS depth profiling for dopant distribution confirmation on request. Process data reported per the agreed plan before wafer release.
60+ dopant species -
the broad dopant selection
From standard n-type and p-type dopants for silicon to specialized implants for SiC activation and compound semiconductor isolation, all available. Inquire for additional species.
Color coding: ■ Key power device dopants ■ Compound semiconductor dopants ■ Standard & specialty
Implantation processes optimized
for power semiconductor devices
Ion implantation for SiC and GaN devices requires fundamentally different process parameters than standard CMOS. Our flows are tuned for the high-temperature requirements and precise doping profiles these devices demand.
SiC MOSFET
SiC MOSFETs require multiple implant steps at elevated temperatures because room-temperature implantation creates amorphous damage layers that cannot be recovered by annealing. Hot implantation (400 to 600 °C) maintains crystallinity through each step.
High-temperature implantation (600 °C) + carbon cap + 1800 °C RTA in one coordinated flow, available as one project.
GaN HEMT
GaN HEMT fabrication uses ion implantation primarily for device isolation, a fluorine or nitrogen implant converts conducting GaN into semi-insulating material, defining the active device area without mesa etching (which improves device reliability).
Implant isolation eliminates the reliability issues of dry-etched mesa sidewalls, a best-practice approach for high-voltage GaN power devices.
Standard and power silicon device implantation flows, p-well, n-well, n+ emitter, p+ collector implants for IGBT structures. Also: base and emitter implants for bipolar transistors, LDMOS source/drain/body, and deep n-well for CMOS isolation.
Simulate before
you implant
Every implant run at Nanosystems JP Inc. is preceded by a detailed simulation of the doping profile. This catches problems before wafers are processed, saving time and cost on expensive SiC and GaN substrates.
SRIM/TRIM + TCAD
dopant profile modeling
RTA to 1800 °C SiC activation
The activation anneal is the final, and most demanding, step in the power device implant flow. We provide RTA activation in the same program, so implant and anneal are planned and specified together.
Ar / N₂ atmosphere
Complete ion implantation
process parameters
| Parameter | Specification | Notes |
|---|---|---|
| Wafer sizes | Samples and pieces; 50, 75, 100, 150, 200, and 300 mm wafers | Non-standard sizes on request |
| Substrate materials | Si, SiC, GaN, GaAs, InP, Ga₂O₃, Sapphire, Glass, InGaAs | All standard semiconductor substrates including ultra-wide bandgap |
| Implant temperature | Room temperature to 600 °C (hot implantation) | Elevated temperature selected per material, species, and dose (typical for high-dose SiC) |
| Dopant species | B, P, As, BF₂, Al, N, H, O, C, Ge, Mg, Si, In, Ca, Ba, He, La, Sn, Cl, Ga, Fe, Cr + more | 60+ species available; inquire for others |
| Dose range | 1 × 10¹⁰ to 1 × 10¹⁷ cm⁻² | Multiple energies for box profiles; high-dose ohmic and threshold adjust both supported |
| Energy range | 0.1 keV to 100 MeV | Plasma immersion (PIII) below 1 keV; medium and high current in the keV range; high-energy implantation to 100 MeV on request (ion species dependent) |
| Machine classes | Medium current, high current, high energy, plasma immersion (PIII) | Selected per species, dose, energy, and profile; dose range and uniformity depend on the class |
| Patterned wafers | Photoresist and hard-mask patterned wafers accepted | Resist thickness reviewed against implant energy and species |
| Wafers with existing metal | Reviewed case by case | Metal-free wafers are preferred for implantation and the anneals that follow; metallized wafers are evaluated before acceptance |
| Tilt angle | 0°: 60° | Suppresses channeling for standard implants; controlled channeling available for deep retrograde profiles |
| Pre-implant simulation | SRIM/TRIM dopant profile modeling included | Profile report before processing |
| RTA max temperature | 1800 °C | Ar and N₂ atmospheres |
| Post-implant verification | Sheet resistance (4-probe), dose uniformity, particle count | Returned with wafer and process data report |
| Beam parallelism | ±0.5° or better | Critical for sub-micron device uniformity; parallel beam architecture |
| Carbon cap processing | Available | Required for SiC anneals >1400 °C |
| SiC activation anneal | 1400 to 1800 °C | Al and N activation for SiC MOSFET wells |
| GaN anneal (RTA, N₂) | 700 to 1000 °C | Hydrogen depassivation of epitaxial Mg-doped GaN; activation of implanted Mg is a separately reviewed development process |
| Surface roughness | Low RMS achieved with carbon cap process | Critical for gate oxide quality on SiC |
Where our ion implantation
is being used
SiC Power MOSFETs
Complete implant flow for 4H-SiC MOSFET fabrication, p-body, n+ source, p+ ohmic, plus 1800 °C activation RTA with carbon cap. For EV inverters, industrial drives, and solar converters.
GaN HEMT & Power Devices
Implant isolation and Si n-type ohmic contacts; Mg p-type regions as a development program (electrical activation of implanted Mg requires a qualified thermal process). E-mode (enhancement mode) GaN transistors for 5G RF and automotive power conversion.
IGBT & Bipolar Devices
P+ collector, N-drift, P-body, N+ emitter implants for IGBT fabrication. Base and emitter implants for bipolar transistors used in automotive and industrial power systems.
MEMS Sensors & Actuators
Piezoresistor implants for pressure sensors (boron in silicon), buried p+ stops for SOI MEMS, sacrificial layer doping, and polysilicon gate doping for capacitive sensors.
SOI & Layer Transfer
High-energy, high-concentration H implantation for Smart Cut™-type SOI substrate preparation. Hydrogen bubble layer formation at precise depth for layer separation and wafer bonding.
Compound Semiconductor Devices
GaAs and InP device isolation by implantation, HBT base/emitter doping, InGaAs channel implants for photodetectors, and GaN-on-Si substrate engineering.
What makes our ion implantation
capability different
Many foundries offer standard room-temperature silicon implantation. What sets this service apart is its ability to handle the complete power device implant flow, including the high-temperature steps and post-implant annealing that SiC and GaN devices demand.
Hot implantation for SiC/GaN
600 °C substrate heating during implantation, a capability that is not widely offered. Hot implantation significantly reduces accumulated lattice damage during high-dose SiC implantation and widens the activation and surface-quality process window.
1800 °C RTA
The highest-temperature process step in SiC device fabrication is performed within the same project. The implant and activation anneal steps are scheduled as one sequence.
60+ dopants ready immediately
We stock over 60 dopant species including rare ones (Ca, Ba, La, Cl) not available at standard foundries. No lead time to source new dopant materials.
Pre-implant simulation included
Every project includes a simulation run, not as an extra charge but as standard. This is how we assess whether the requested doping profile is compatible with the proposed implant conditions before a wafer is loaded.
From 1 wafer, no minimum lot
Power device R&D and prototyping doesn't need 25-wafer lots. We process single wafers and small batches, making us accessible for academic research, startups, and low-volume production alike.
Integrated with full process flow
Ion implantation is followed directly by our etching, deposition, CMP, and bonding services. One continuous project, lower contamination risk, no coordination overhead for you.
Start your project.
Initial response typically within one business day.
Share your process requirements, substrate, and production volume. A Nanosystems JP Inc. engineer will give an initial response typically within one business day. Full quote typically within 7-10 business days, subject to project complexity and NDA requirements.