At Nanosystems JP Inc., we offer annealing services after ion implantation, thin film deposition, or bonding is a critical step that determines final device performance. The wrong atmosphere or temperature causes oxide growth, surface roughness, or incomplete dopant activation.
Nitrogen (N₂) Annealing
Controlled N₂ atmosphere prevents oxidation while enabling dopant activation, film densification, and ohmic contact formation. The standard atmosphere for post-implant annealing of silicon CMOS devices, PECVD SiO₂/SiN film densification after deposition, and metal contact sintering. N₂ is inert at most semiconductor process temperatures, providing a clean, contamination-free environment for sensitive device layers.
Hydrogen (H₂) / Forming Gas
H₂ atmosphere or forming gas (typically 5–10% H₂ in N₂) passivates interface traps at the Si/SiO₂ gate oxide interface by bonding hydrogen to dangling silicon bonds. Reduces interface trap density (Dit), improving threshold voltage stability and carrier mobility in MOS transistors. Also used for defect reduction in compound semiconductor epitaxial layers and reduction of native oxides on metal surfaces before bonding.
Vacuum Annealing
Highest-purity annealing environment, eliminates all reactive gases including trace oxygen, nitrogen, and water vapor. Essential for precise stoichiometry control in complex oxide thin films, bonding interface improvement before direct wafer bonding, and applications where even trace atmospheric contamination at high temperature would alter film composition. Dopant activation under vacuum provides the cleanest activation environment for research devices.
Rapid Thermal Annealing (RTA)
Rapid lamp-based heating to temperatures up to 2000°C under Ar or N₂, enabling very short annealing times (seconds to minutes) that activate dopants while preventing unwanted dopant diffusion in shallow junction devices. SiC dopant activation requires 1400–1800°C in Ar, the highest temperature annealing required in power device fabrication. GaN Mg acceptor activation at 700–1000°C. Si shallow junction activation at 900–1100°C without dopant diffusion.
SiC Wafer Annealing
Dedicated annealing service for silicon carbide, the most thermally demanding step in power device fabrication. Al (p-type) and N (n-type) implants in 4H-SiC require 1400–1800°C activation in Ar atmosphere to achieve full electrical activation. Without high-temperature annealing, implanted SiC dopants are nearly electrically inactive regardless of dose. Our process achieves >80% activation efficiency for Al and N in 4H-SiC at the required temperatures.
Carbon Cap Annealing
Before high-temperature SiC annealing, a carbon cap layer is deposited on the wafer surface to prevent silicon evaporation and the step-bunching surface morphology that degrades gate oxide quality. After the anneal, the carbon cap is removed, leaving a smooth low-RMS surface. Carbon cap thickness is precisely controlled because too thin a cap fails to prevent Si evaporation while too thick a cap causes its own surface defects during removal.