SUBSTRATE SPECIFICATION

Fused Silica Wafers
& Substrates

Precision-grade SiO₂ wafers for optical, MEMS, thin film, and photonic applications - available in all major purity classifications, standard and custom dimensions, with optical surface finishes to your specification.

Have full specs ready? Submit a detailed Technical RFQ →

SiO₂ / Fused Silica JGS1 · JGS2 · JGS3 Synthetic Quartz UV-IR Transmission Custom Thickness TGV Compatible
4
Purity grades
available
1"-6"
Standard wafer
diameter range
Ra<0.5
High-precision
surface finish (nm)
±10µm
Custom thickness
tolerance
OVERVIEW

From substrate procurement
to finished device

Nanosystems JP Inc. supplies fused silica wafers and substrates to support device development across optics, MEMS, semiconductor packaging, and photonics. We handle standard grade procurement and custom specifications - including non-standard diameters, tailored thicknesses, and specified surface finishes - as part of a complete fabrication engagement. When your project requires TGV drilling, thin film deposition, lithography, or dicing on the same material, those steps are managed as one project.

PURITY GRADES

All major fused silica grades

Fused silica is produced by several methods, each yielding different OH content and spectral performance. The table below outlines the four primary grades and their typical application domains. Grade designations follow the JGS classification system widely used across Asia and internationally.

Grade Production Method OH Content UV Cutoff IR Cutoff Primary Applications
JGS1 Oxyhydrogen flame synthesis (synthetic SiO₂) ~200 ppm ~170 nm ~2.5 µm Deep-UV optics, excimer laser components, UV lithography windows, photomask substrates
JGS2 Gas-refined natural quartz fusion ~150 ppm ~220 nm ~2.5 µm Visible and near-UV optics, MEMS device substrates, hermetic packaging windows
JGS3 Electric fusion of natural quartz <10 ppm ~260 nm ~3.5 µm Mid-IR and thermal imaging optics, infrared spectroscopy windows, IR sensor covers
Synthetic Quartz CVD / flame hydrolysis (ultra-pure) Grade-specific ~160 nm ~2.5 µm DUV lithography, high-power laser systems, semiconductor photomasks, precision interferometry

Cutoff wavelengths are indicative at typical transmission threshold (≥10%). Actual performance varies by sample thickness and surface condition. Contact us if your drawing references a regional grade name or alternative designation, we can confirm the appropriate equivalent.

STANDARD SPECIFICATIONS

Wafer sizes, thickness &
surface finish options

Standard stock covers the most common wafer sizes and finish grades. Custom dimensions are available on request with typical lead times discussed at inquiry stage.

⬛ Wafer Diameter

  • 1 inch (25.4 mm)
  • 2 inch (50.8 mm)
  • 4 inch (100 mm)
  • 6 inch (150 mm)
Custom diameters and rectangular / square chip substrates available on request.

📏 Thickness

  • Standard stock: 200 µm - 2 mm
  • Ultra-thin: <200 µm (custom)
  • Thick substrates: >2 mm (custom)
  • Tolerance: ±10 µm on custom orders
Thickness uniformity <5 µm TTV available on precision grades.

🔬 Surface Finish

  • Standard optical polish - Ra <1 nm (scratch-dig specified independently)
  • High-precision polish - Ra <0.5 nm (scratch-dig specified independently)
  • Single-side or double-side polished
  • Unpolished / as-cut (for non-optical use)
Custom flatness specifications and surface quality grades available.

📐 Additional Options

  • SEMI-standard orientation flat - 4" and 6" wafers
  • Notched wafers on request
  • Edge polish and edge exclusion to spec
  • Wafer inspection report available
Laser marking and cassette/FOUP-compatible packaging available for larger lots.
CUSTOM PROCUREMENT

Non-standard specifications

Standard grades do not always match design requirements. We supply custom fused silica wafers tailored to your project, and coordinate any additional processing steps as a single engagement.

Custom specification capabilities

Submit your drawing or spec sheet and we will quote substrate supply, surface processing, and any downstream fabrication steps - managed as one project at Nanosystems JP Inc.

  • Custom thickness specified to ±10 µm tolerance
  • Custom diameter or square / rectangular substrates
  • Specified surface quality grade (Ra, scratch-dig, or flatness class)
  • Anti-reflection, high-reflection, or metal film coatings
  • ITO (indium tin oxide) deposition for electrooptic applications
  • Pre-drilled TGV for hermetic packaging or interposer applications
  • Combined lithography, etching, or thin film on the same wafer
  • Small R&D lots accepted - no minimum order quantity
Program Sketch

One wafer, annotated

The whole program on one drawing: polish grade, tolerances, through-glass holes, and chip-scale formats.

Fused silicaDSP · optical polishunfilled TGV<5µm TTVprecision grade±10µmthickness tol.chip-scale rectanglesPolish, pattern, TGV, and dice under one program
The fused silica wafer program at a glance
APPLICATIONS

Where fused silica is specified

Fused silica is selected when silicon or borosilicate glass cannot meet the optical, thermal, or chemical requirements of the application. Common use cases include:

MEMS device substrates Through-glass via (TGV) interposers Hermetic packaging windows UV / visible / IR optical windows Thin film deposition substrates (ALD, CVD, PVD) Photolithography masks and reticles Excimer laser and high-power laser optics Biomedical and microfluidic devices RF and high-frequency substrates (low dielectric loss) Precision interferometry and metrology Semiconductor photomask blanks Cryogenic optical applications
🔲

TGV Interposers

Fused silica is our preferred glass for TGV (through-glass via) formation. Its low CTE, UV transparency, and chemical resistance make it well-suited for 2.5D packaging and optical interposer applications. We supply the substrate and drill the vias as a coordinated service.

Min via 20µm 510×510mm panel Low CTE
💡

Photonic & Optical

The broad transmission window (UV to mid-IR), negligible autofluorescence, and low thermal expansion make fused silica the standard choice for optical windows, waveguide substrates, and components in high-power laser systems.

160nm - 3.5µm CTE ≈0.55 ppm/°C Low autofluorescence
🧬

Biomedical & Microfluidics

Chemical inertness, optical clarity across UV/visible wavelengths, and compatibility with standard semiconductor etching processes make fused silica a strong substrate choice for lab-on-chip devices, biosensor windows, and implantable optical components.

UV transparent Chemically inert DRIE compatible
WHY NANOSYSTEMS JP INC.

One project for substrate
and fabrication

01

Multi-region supply chain access

We source from both Japanese domestic and internationally recognized fused silica supply chains, giving you access to the appropriate grade and format in one project.

02

Substrate and fabrication in one project

When your fused silica wafer needs TGV drilling, thin film deposition, lithography, etching, or dicing, those steps are managed as one project. One quote, one point of contact.

03

R&D and small-lot quantities

No minimum order quantity for standard grades. Prototype and R&D quantities are accepted - from a single wafer up to engineering lot quantities - with the same process rigor as production orders.

04

Grade cross-referencing and specification support

If your drawings reference a regional grade name or a datasheet specification rather than a JGS grade, our team can confirm the appropriate supply and verify compatibility with your process requirements.

Request fused silica substrates.
Initial response within one business day.

Share your grade requirement, wafer size, thickness, surface finish, and quantity. A Nanosystems JP Inc. engineer will give an initial response within one business day. Full quote typically within 7-10 business days, subject to custom specification requirements and NDA.

sales@nanosystemsjp.co.jp · NDA available on request · Initial response within one business day

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Initial engineering response: typically within one business day. NDA available.
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Services & Industries
Capabilities Overview
Substrates
Substrate & WafersSi, SiC, GaN, glass, sapphire Fused Silica WafersQuartz · borosilicate · low CTE Glass ProcessingDrilling, etching, polishing PI Film & SUS Sensor FabRoll-to-roll · sensor patterning
Front-End
Mask FabricationGDS to chrome mask, DRC PhotolithographyE-beam 20 nm to 500×600 mm NanoimprintingUV & thermal NIL Thin Film DepositionPVD, CVD, ALD, MBE ALD CoatingConformal oxides, nitrides PECVD DielectricsSiO₂, SiN, SiON, a-Si TFT & BackplaneIGZO · Glass · Display LiftoffMetal pattern · shadow mask ElectroplatingCu TSV fill, DPC, LIGA Electroforming & LIGANi shims, meshes, microstructures EtchingICP-RIE, DRIE >50:1 ICP-RIE EtchingSi, oxide, III-V, SiC, quartz MEMS FoundrySensors, actuators, microfluidics Microchannel CoolingEtched, bonded, heater test chips Thermal Test ChipsHeater dies, multi-zone, RTD Temperature SensorsPt/NiCr RTDs, thermocouples AnnealingN₂ / H₂ / vacuum / RTA Ion ImplantationB / P / As / Al / N implant CMP & GrindingCu CMP, 50 µm thinning Wafer ThinningTo 50 µm on carriers Patterned Test WafersCustom CMP and process evaluation wafers Daisy-Chain Test DiesDummy dies, chains, bump options DicingBlade, stealth laser Stealth & Laser Dicing300 mm Si and glass, SDBG Wafer CleaningRCA, plasma, megasonic Cleaning ChemistryPiranha, SC-1, SC-2, RCA
Advanced Packaging
Wafer BondingHybrid, eutectic, fusion Anodic BondingGlass to silicon, cavities MEMS Cap WafersCavities, ports, seal lands, bonded TSV FabricationHigh AR, Cu fill InterposersSi and glass, TSV/TGV + RDL TSV RevealBackgrind → etch → CMP TGV FabricationThrough-glass via Glass TGV CouponsHole-only to routed prototypes RDL FabricationBCB / PBO / PI + damascene Packaging & AssemblyWire bond, flip-chip Flip-Chip BondingTC, reflow, AuSn, underfill 3D / 2.5D PackagingTSV + RDL + UBM + C4 AuSn BumpPVD lift-off, fluxless Laser SubmountsSi/AlN submounts, optical benches Indium BumpEvap lift-off · cryo/quantum UBM DepositionTi/Pt/Au · adhesion-barrier-Au Cu Pillar & SnAg BumpingPillars with SnAg caps, SnAg bumps Gold BumpEvap & plated · Au-Au TC AuGe / AuSi361/363°C eutectic die attach High-Pb Bumps95Pb5Sn · hi-rel C4 SLID / TLPCu/Sn · Au/In · Ag/In Al-Ge Sealing424°C · CMOS-friendly MEMS Ohmic ContactsGaAs · GaN · RTA + TLM SiC ProcessingContacts, implant, 1800 °C anneal GaN & III-VGaN, GaAs, InP processing Cryo / UHV MetalAuSn · Ti/Pd/Au · rings Optical AccessWindows · meshes · holes Vapor CellsDRIE + bond · unfilled TFOI WafersQuartz-on-Si · LNOI Biochip & MicrofluidicsGlass 500×600 mm, NIL SiPho PackagingTSV · RDL · UBM · C4 for PIC Photonic DevicesSiN/SOI waveguides, gratings
Industries
AI & HPC PackagingCoWoS-style, 2.5D / 3D Silicon PhotonicsSOI · AuSn · TSV interposer AutomotiveMEMS sensors, SiC power Life SciencesLab-on-chip, biosensors All Industries → Request a Quote →