Oxide Semiconductor TFT & Display Backplane Fabrication
Complete foundry services for IGZO and oxide semiconductor TFT devices on glass substrates - from initial prototyping through production-scale fabrication. We provide multi-layer metal wiring, thin film deposition, photolithography, dry and wet etching, organic interlayer dielectric coating, and full process integration for TFT backplane applications.
What is Oxide Semiconductor TFT?
The fundamental switching element in every active-matrix display and sensor array - and why IGZO has become the technology of choice for next-generation backplanes.
Thin-film transistors (TFTs) are the fundamental switching elements that drive active-matrix displays and sensor arrays. In a TFT backplane, each pixel or sensing element is controlled by an individual transistor fabricated directly on a glass or flexible substrate, enabling precise, independent control of millions of elements simultaneously.
Oxide semiconductor TFTs - most commonly based on IGZO (Indium-Gallium-Zinc Oxide, InGaZnO₄) - have emerged as the leading technology for next-generation flat-panel displays, replacing conventional amorphous silicon (a-Si) TFTs in an increasing number of applications. The key advantages of IGZO over a-Si include significantly higher carrier mobility (typically 10-50 cm²/V·s compared to <1 cm²/V·s for a-Si), enabling faster pixel switching and smaller transistor footprints. Additionally, IGZO can be deposited at relatively low temperatures by RF sputtering, making it compatible with large-area glass substrates and even certain flexible substrates.
A typical IGZO TFT is fabricated using a bottom-gate, etch-stopper (ES) architecture. In this structure, the gate electrode is deposited first on the glass substrate, followed by the gate insulator, IGZO channel, etch stopper, and source/drain electrodes. Wiring layers (up to four conductor layers in total, counting gate, source/drain, wiring, and ITO) are then built up on top of the TFT, separated by planarizing interlayer dielectric (ILD) coatings, with via connections between layers. The top metal layer is often ITO (Indium Tin Oxide), which serves as the pixel electrode or sensing electrode.
At Nanosystems JP Inc., we offer comprehensive TFT backplane fabrication services covering every step of this complex process - from gate metal deposition through final passivation and dicing. We support the full range of development stages, from small-lot R&D prototyping on approximately 100 mm square glass coupons to larger-scale fabrication on panels up to 400×300 mm.
Process Capabilities
A complete suite of thin film, patterning, and packaging processes tailored for oxide semiconductor TFT backplane fabrication on glass substrates.
Metal & Oxide Sputtering
DC and RF magnetron sputtering for gate metals (Mo alloy, MoNb), source/drain metals (Mo alloy, Al alloy including Al-Nd), transparent conductors (amorphous ITO / polycrystalline ITO / IZO), oxide semiconductors (IGZO, InGaZnO₄), and barrier/adhesion layers (Cr, Ti). Multi-target configurations enable sequential multi-layer stack deposition without breaking vacuum - critical for interface quality. Reactive sputtering modes available for compound film formation.
Plasma-Enhanced CVD (P-CVD)
P-CVD deposition of silicon nitride (SiNx) and silicon oxide (SiOx) for gate insulators, etch stoppers, passivation layers, and final protective overcoats. SiNx provides excellent moisture and ionic contamination barriers - critical for long-term IGZO device stability. SiOx is used as etch-stopper layers due to favorable etch selectivity. Small-format substrates or silicon wafers can also be accommodated for process development.
Photolithography (PEP)
Stepper and contact aligner exposure systems for multi-layer TFT patterning at 5 μm line/space resolution. The complete photolithography cycle - resist coating, pre-bake, alignment, exposure, post-exposure bake, development, and inspection - is performed for each mask layer. A typical 4-metal-layer IGZO TFT requires 10-11 photomask levels. Mask layout design support (CAD) available upon request.
Dry & Wet Etching
Reactive ion etching (RIE) with fluorine-based chemistry for precise patterning of SiNx, SiOx, and dielectric layers. Wet etching for metals (Mo alloy, Al alloy), oxide semiconductors (IGZO), and transparent conductors (ITO) using optimized etchant chemistries for high selectivity and minimal undercutting. Etch selectivity between source/drain metal and etch-stopper layer is a critical parameter - our processes are tuned for clean, damage-free interfaces.
Organic ILD Coating
Spin-coated acrylic and polyimide resins for interlayer dielectric planarization. Thick organic ILD coatings (typically 1-30 μm) provide excellent planarization of step height variations between metal layers. Photosensitive grades of both materials are available in the offered flow - via-holes are formed directly by exposure and development without a separate etch step, simplifying the process flow and reducing total mask count.
Dicing, Inspection & Finishing
Precision glass cutting to custom dimensions with edge polishing for clean, chip-free edges. Substrates can be cut from large-format panels to individual device chips. Optical inspection, profilometry, and film thickness measurement are available throughout the fabrication process to ensure quality at each stage.
TFT Architecture - Bottom-Gate Etch-Stopper Structure
The most widely adopted architecture for oxide semiconductor TFT backplanes in commercial display manufacturing - chosen for its excellent balance of device performance, process robustness, and manufacturing yield.
The etch-stopper layer deposited directly on the IGZO channel protects it from damage during source/drain metal etching - a critical step that determines the quality and reliability of the finished device. Multi-layer metal wiring (up to 4 layers) is built above the TFT, separated by planarizing organic ILD coatings.
| Layer | Function | Material Options | Process |
|---|---|---|---|
| M1 | Gate Electrode | Mo alloy | Sputtering + Wet Etch |
| GI | Gate Insulator | SiNx, SiOx | P-CVD |
| IGZO ★ | Active Channel | InGaZnO₄ | Sputtering + Wet Etch |
| ES | Etch Stopper | SiOx | P-CVD + Dry Etch |
| M2 | Source / Drain | Mo alloy | Sputtering + Wet Etch |
| PAS | Passivation | SiNx | P-CVD + Dry Etch |
| ILD-1 | Interlayer Dielectric | Acrylic or Polyimide | Spin-coat + PEP |
| M3 | Wiring Layer 3 | Mo alloy, Al alloy | Sputtering + Wet Etch |
| ILD-2 | Interlayer Dielectric | Acrylic or Polyimide | Spin-coat + PEP |
| M4 | Top Electrode (ITO) | ITO | Sputtering + Wet Etch |
| FP | Final Passivation | SiNx / SiOx | P-CVD + Dry Etch |
★ IGZO active channel layer - highlighted. Layer count and material selection customizable. 3-layer configurations (without ILD-2 and M4) also supported.
Process Design Rules & Guidelines
Starting reference values for TFT backplane layout design, representing typical achievable specifications. All values finalized during the process design stage based on your specific device requirements.
| Min. line/space (metals) | 5 μm L/S |
| Organic ILD min. feature | 10 μm |
| Exposure method | Stepper / Contact aligner |
| Resist types | Positive & negative |
| Gate (M1) | Mo alloy |
| Source/Drain (M2) | Mo alloy |
| Wiring (M3) | Mo alloy / Al alloy |
| Electrode (M4) | ITO (transparent) |
| Gate insulator (GI) | SiNx recommended, SiOx option |
| Etch stopper (ES) | SiOx (standard) |
| Passivation (PAS/FP) | SiNx (moisture barrier) |
| Max GI thickness | Up to ~1 μm SiNx |
| Deposition method | RF magnetron sputtering |
| Target material | InGaZnO₄ (ceramic) |
| Post-deposition anneal | N₂ or air atmosphere |
| Channel patterning | Wet etch (dilute acid) |
| Acrylic resin (thick) | Up to ~30 μm |
| Polyimide resin (thin) | Up to ~3 μm |
| Both photosensitive | Direct via formation |
| Min. via size | ~10 μm |
| S/D etch stop | Wet etch stops on SiOx ES - critical interface |
| IGZO sensitivity | H₂, moisture, process damage managed carefully |
| RIE selectivity | SiNx/SiOx selectivity used at multiple steps |
Typical Process Flow
A representative 10-11 photomask process for a 4-metal-layer IGZO TFT backplane. The exact number of mask levels depends on your device architecture and can be adjusted during process design.
Cleaning
(M1)
→ Wet Etch
(GI)
Channel
→ Wet Etch
(ES)
→ Dry Etch
(M2)
→ Wet Etch
(PAS)
→ Dry Etch
→ Cure
→ Wet Etch
→ Cure
(M4)
→ Wet Etch
(FP)
Dice → Ship
Application Areas
The high mobility, low off-current, and large-area uniformity of IGZO make it attractive for any application requiring an active-matrix switching array on a glass or transparent substrate.
Flat Panel Displays (LCD & OLED)
High-mobility IGZO TFTs enable higher-resolution, lower-power display backplanes compared to a-Si. IGZO's low off-state leakage current is particularly advantageous for OLED displays, enabling more stable pixel current driving and longer panel lifetime. Our process suite supports color filter (CF) patterning, tapered electrode edge profiles for improved edge cover layer reliability, and ITO surface treatment, key requirements for OLED backplane integration.
Flexible & Large-Area Electronics
IGZO can be deposited at relatively low temperatures, making it compatible with certain flexible substrate processes. Applications include e-paper, digital signage, large-format information displays, and emerging flexible sensor platforms.
Medical & Industrial Sensor Arrays
Active-matrix TFT backplanes are used as readout substrates for X-ray flat-panel detectors (FPDs), biosensor arrays, and fingerprint recognition modules. The TFT array converts the sensed signal from each pixel element into sequential electrical output.
R&D Prototyping & Device Evaluation
We support small-lot fabrication for university research groups and corporate R&D teams developing novel oxide semiconductor devices. TEGs, TFT characteristic evaluation substrates, and process optimization vehicles with flexible lot sizes starting from 1-3 substrates.
Substrate & Prototyping
Flexible substrate options and lot sizes to support projects at every stage of development, from early-stage research through production qualification.
Glass Substrates
Alkali-free glass (e.g., borosilicate) in standard thicknesses of 0.5 mm and 0.7 mm. Custom sizes from approximately 100 mm square for prototyping up to 400×300 mm for scale-up. Customer-supplied substrates also accommodated.
Prototype to Production
Small-lot prototyping with as few as 1-3 substrates. We provide process design support, mask layout review, and CAD assistance to help bring your device concept to fabrication. Once established, we scale to repeatable production runs.
Typical Lead Time
Approximately 9-13 weeks from inquiry to shipment for an initial prototyping lot, including process design, mask procurement, multi-layer fabrication, inspection, and reporting. Lead times vary by project complexity.
Our Approach - From Concept to Fabrication
At Nanosystems JP Inc., we understand that TFT backplane fabrication is not simply a sequence of individual process steps - it is a tightly integrated process flow where each layer must be designed and optimized in the context of the complete device. A change in gate insulator thickness affects threshold voltage; a change in etch-stopper composition affects S/D contact resistance; a change in passivation conditions affects long-term device stability.
That is why we take a collaborative, device-level approach to every TFT project. When you bring us your device concept, we don't simply run recipes - we work with you to design a process flow that meets your specific performance targets while remaining within the constraints of manufacturable processing. Our team has deep experience in multi-layer thin film integration and can advise on layer stack design, material selection, thermal budget management, and process sequencing. In addition to the standard BG-ES TFT flow, we support color filter (CF) patterning on glass, water-repellent bank formation, and tapered electrode edge processing for OLED-compatible backplane integration.
We welcome inquiries at any stage - whether you have a fully designed mask set ready for fabrication, or you are at the concept stage and need help defining the layer stack and process flow. Please contact us to start the discussion.
Start your TFT project.
Initial response within one business day.
Share your device concept, substrate requirements, and target process flow. A Nanosystems JP Inc. engineer will give an initial response within one business day. Full quote typically within 7-10 business days, subject to project complexity and NDA requirements.