Silicon & Glass Interposer
Fabrication for AI Accelerators
Full-stack 2.5D and 3D interposer packaging - TSV, TGV, RDL, hybrid bonding, and micro-bumps - from a single pure-play foundry. Single-wafer R&D through repeat production on an established baseline.
ratio (DRIE)
via diameter
bond align.
510×510 mm (TGV panels)
AI silicon needs a new kind of packaging foundry.
Packaging capacity is the constraint
Every next-generation AI accelerator - from GPUs to custom TPUs - requires high-density silicon interposers to connect logic dies with HBM memory stacks. But major OSATs have long lead times, high minimum volumes, and limited flexibility for development lots. For startups and scaling AI chip companies, this means months of delays at the most critical phase of the product cycle: first silicon validation and early production ramp.
Single-source interposer foundry, single wafer to volume
As a pure-play foundry, Nanosystems JP Inc. manages your complete interposer process flow through one project - covering TSV/TGV etching, copper fill, RDL patterning, and bonding through to final bumped wafer delivery. No minimum order quantity. All steps managed in one continuous project. Development lots start from a single wafer, quotes within 7-10 business days, and mutual NDA protection from first inquiry.
High-density TSV interposers for AI & HPC.
For GPU/HBM integration, chiplet architectures, and high-bandwidth computing applications requiring the densest possible interconnect.
TSV Fabrication
High aspect ratio through-silicon vias by DRIE Bosch process with conformal dielectric isolation, Ti/Cu barrier-seed deposition, and bottom-up copper electroplating for full fill.
TSV Reveal
Complete via reveal (backside exposure of previously formed TSVs) process: temporary bonding to carrier wafer, backgrinding to target thickness, dry etch Cu exposure, and dielectric deposition with final CMP.
RDL Fabrication
Redistribution layer patterning via single and double Cu damascene processes with polymer passivation layers. Enables fine-pitch fan-out routing between die and TSV arrays.
Hybrid Bonding
Dielectric-to-dielectric and metal-to-metal Cu-Cu bonding for highest-density 3D die stacking. Enables interconnect pitches below 10µm moving toward sub-1µm.
TGV interposers for RF, photonics, and panel scale.
When your application demands superior RF insulation, tunable CTE, optical transparency, or panel-level cost economics.
TGV Fabrication
Through-glass via formation with four profile options - hourglass, straight, tapered, and blind (BGV) - to match your interconnect and deposition requirements.
Copper Metallization
Both conformal Cu coating (thin-wall lining for signal routing) and complete Cu fill (solid plug for power delivery and thermal paths). Barrier/seed by PVD.
Panel-Level Processing
Process glass substrates at panel scale - up to Gen.4 (510×510 mm TGV panels) - yielding several times (basis: design, panel utilization and yield, per program) more interposers per run versus 300mm silicon wafers. Fundamentally changes the cost-per-interposer equation.
Silicon or glass? We fabricate both.
Two interposer platforms, one foundry. We help you select the right substrate for your application - or prototype both.
| Property | Silicon Interposer | Glass Interposer |
|---|---|---|
| Best for | AI/HPC, HBM, chiplets | RF/mmWave, photonics, AiP |
| Via technology | TSV (DRIE) | TGV (laser / etch) |
| Max aspect ratio | >50:1 | Up to 10:1 |
| Min. via diameter | 5 µm | 30 µm |
| RF loss tangent | High (semiconductor) | Very low (insulator) |
| CTE | ~2.6 ppm/°C (fixed) | 3-9 ppm/°C (tunable) |
| Optical transparency | Opaque | Transparent (visible + NIR) |
| Max substrate size | 300mm wafer | 510×510 mm (TGV panels) panel (Gen.4) |
| Cost at volume | Higher (wafer-level) | Lower (panel-level) |
| Bonding options | Cu-Cu thermocompression, or dielectric-plus-metal hybrid bonding as a separate route, Eutectic | Anodic, Eutectic, Direct |
Full process support - available for both platforms.
Full process parameters.
TSV Fabrication
Silicon interposer via process
| Etch method | DRIE (Bosch process) |
| Aspect ratio | >50:1 |
| Via diameter | 5-100 µm |
| Via depth | >100 µm |
| Dielectric liner | PECVD SiO₂ · Al₂O₃ ALD |
| Barrier / seed | Ti/Cu PVD (TaN/Ta optional) |
| Cu fill | Full-fill electroplating |
| CMP dishing | <0.5 µm typical |
| Wafer size | 100mm-300mm |
TGV & Glass Interposer
Glass interposer via process
| Via formation | Laser / wet etch |
| Aspect ratio | Up to 10:1 |
| Min. via diameter | 30 µm |
| Via profiles | Hourglass · Straight · Tapered · Blind |
| Cu fill modes | Conformal · Full fill |
| CTE range | 3-9 ppm/°C (tunable) |
| Panel sizes | Up to 510×510 mm (TGV panels) (Gen.4) |
| Wafer sizes | 100mm-300mm |
| Bonding options | Anodic · Eutectic · Direct |
Why Nanosystems JP Inc.
No minimum order quantity. Start with a single development wafer and scale to production volumes when ready.
Our engineers review your design and provide a detailed technical quote - process flow, timeline, and pricing - within 7-10 business days.
One project covers every process step. Single project, single PM, single point of contact, no fragmentation between process steps.
Mutual NDA executed before any design data is shared. All IP handled confidentially with full traceability.
Who this is for.
GPU & TPU Interposers
Silicon interposers connecting AI accelerator logic dies with HBM memory stacks. High-density TSV arrays with >10,000 connections/mm² enable the bandwidth required for next-gen training and inference chips.
Custom AI ASICs
Startups and hyperscalers designing custom silicon for specific AI workloads need a packaging foundry that accepts development quantities, iterates fast, and scales without forcing requalification of the process.
5G / mmWave & Co-Packaged Optics
Glass interposers for RF front-end modules and silicon photonics transceivers co-packaged with switch ASICs. Low-loss substrates for data center connectivity.
HBM Integration
Stacked DRAM integration with logic dies via silicon interposers. Fine-pitch micro-bumps and high-density TSVs deliver the memory bandwidth that AI workloads demand.
HPC & Networking Chiplets
Multi-die configurations with heterogeneous process nodes unified on a single interposer. Both silicon and glass options available depending on bandwidth and RF requirements.
R&D & Prototyping
University research groups and R&D labs. Single-wafer prototyping with full foundry support and process flexibility unavailable from volume OSATs.
Submit your design.
Initial response within one business day.
Send us your GDS, process specifications, or even a concept sketch. Our engineers review personally and respond with a detailed technical quote including process flow, timeline, and pricing.
📧 sales@nanosystemsjp.co.jp
🔒 Mutual NDA available before data transfer
📋 All designs handled with full confidentiality
⏱ Initial response within one business day · Full quote within 7-10 days