Lift-Off
Patterning
PVD sputtering and e-beam evaporation are the deposition methods used in lift-off patterning flows. We offer the full lift-off service - resist, exposure, PVD deposition, and solvent strip - for Au, Pt, TiN, and AuSn multi-layer stacks.
resolution
no wet etch needed
definition
supported
Four steps from bare wafer
to patterned metal
Lift-off defines metal features by patterning resist first, depositing metal over the entire wafer, then dissolving the resist to leave metal only where the wafer surface was exposed. It avoids wet or dry etching of the metal entirely.
Resist Coating & Exposure
A positive photoresist is spin-coated on the wafer and exposed using the appropriate tool for the required feature size: contact aligner for features above 2µm, stepper for finer geometries. The exposure dose is tuned to produce a slight undercut in the developed profile, critical for clean metal separation during lift-off.
Develop & Inspect
The exposed resist is developed to open windows where metal will be deposited. The sidewall profile - slightly re-entrant (undercut) - is verified by SEM cross-section for critical processes. The undercut prevents the deposited metal from bridging between the resist sidewall and the substrate, ensuring a clean break during lift-off.
PVD Metal Deposition
Metal is deposited by PVD (sputtering or evaporation) over the entire patterned wafer. The deposition must be sufficiently directional so metal on the resist sidewalls is thin and discontinuous, allowing solvent to penetrate. Step coverage and deposition angle are controlled to optimize this. Au, Pt, Ti, TiN, AuSn, Ni, NiCr, and Al are all available.
Solvent Lift-Off
The wafer is immersed in a solvent bath, commonly NMP (N-methyl-2-pyrrolidone) or acetone for standard photoresists, which dissolves the underlying resist layer and enables the overlying metal to lift off. This process removes unwanted material without the need for metal etching. Gentle agitation, including controlled ultrasonic assistance when appropriate, may be used to promote complete lift-off while preserving pattern integrity. The result is a patterned metal layer with well-defined features.
When wet etching is not an option
Lift-off is the right patterning method when the metal cannot be wet-etched - either because no selective etchant exists, because etch chemistry would damage underlying layers, or because the metal stack is too thin to mask reliably.
Noble metals
Au and Pt have no practical wet etchants compatible with photoresist. Aqua regia etches Au but attacks almost everything else. Lift-off is the standard patterning method for Au and Pt electrodes, bond pads, and contact metallization.
AuSn eutectic bumps
AuSn 80/20 eutectic solder cannot be wet-etched without destroying the precise Au:Sn ratio required for 278°C eutectic behavior. Lift-off of a PVD Au/Sn multi-layer stack is the standard method for AuSn bump definition.
Underlying layer sensitivity
On devices where etch chemistry would attack a previously deposited layer - III-V compound semiconductor surfaces, piezoelectric films, or chemically sensitive bio-interfaces - lift-off avoids all wet metal etch steps entirely.
When lift-off is the right choice
Neither lift-off nor etching is universally better. The right choice depends on the metal, the feature geometry, and the underlying layers. This table summarizes the key decision factors.
| Factor | Lift-Off | Wet Etching | Dry (Plasma) Etching |
|---|---|---|---|
| Au, Pt, Ir, AuSn | ✓ Best option - no reliable etchant exists | ✗ No practical etchant | ✗ Very slow, re-deposition, chamber contamination |
| Al, Ni, Cr | ✓ Works well | ✓ Reliable, fast | ✓ Good option |
| Fine-pitch electrodes (<5µm) | ✓ Excellent - sharp sidewalls, no undercut | ✗ Isotropic etch causes undercut of features | ✓ Good, but mask required |
| Thick metal (>2µm) | ✗ Difficult - metal thickness must be < resist undercut | ✓ No thickness limit | ✓ No thickness limit |
| Sensitive underlying layers | ✓ No etch step on the deposited film; resist and solvent compatibility confirmed per stack | ✗ Etchant may attack underlying material | ✗ Plasma can damage gate oxides, sensors |
| Multi-layer metal stacks | ✓ All layers deposited in one PVD run, lifted together | ✗ Each layer needs its own etch step | ✗ Each layer needs its own etch step |
| Edge sharpness | ✓ Defined by resist, not etch isotropy | ✗ Undercutting degrades edge definition | ✓ Good vertical sidewalls possible |
where evaporation stops and plating starts
For bumps and thick metal, the competitor is not etching but electroplating, and the boundary between them is geometric and economic, not a matter of preference. Here is the honest version.
The Geometry Limit
Clean lift-off wants the deposited metal no more than about one-third to one-half of the resist thickness, and as material accumulates on the resist top, the aperture pinches off, self-limiting the deposit. In normal practice that caps evaporated features around 5-10µm, perhaps 15µm with a thick bilayer resist on a cooled, well-collimated tool. Anything taller, or anything needing a straight plated sidewall instead of lift-off's truncated-cone profile, belongs to plating through a resist mold. That is why Cu pillars, thick SnAg, and tall Ni are plated, essentially always.
The Economics Limit
Evaporation coats the whole chamber and most of the material is thrown away, so it stays economical exactly where this site uses it: thin layers, precious metals whose overspray is reclaimed, and low wafer counts. Plating deposits only where current flows, scales with bath capacity, and wins on throughput the moment layers get thick or volumes get large. The crossover is why our UBM, AuSn, indium, and gold fine-pitch work runs by evaporation while Cu, thick solder, and tall gold run through the plating line, one flow, two tools, each where it is honest.
| Your requirement | Route | Why |
|---|---|---|
| Pt, AuSn, AuGe, In, high-Pb, alloy stacks | Evaporation + lift-off | No practical etch or plating chemistry; composition by layer ratio |
| Sub-µm to ~5µm features, pristine interfaces | Evaporation + lift-off | Resist-defined edges, all layers in one vacuum |
| Bumps taller than ~10µm | Plating through resist | Beyond the lift-off geometry cap |
| Cu pillar, thick SnAg, tall Ni | Plating through resist | Straight sidewalls, thickness, throughput |
| Large volumes of thick metal | Plating through resist | Deposition only where needed; bath economics |
| Resist or solvents unacceptable (released MEMS, organic layers) | Shadow mask evaporation | Si / Mo stencil, no resist ever touches the device; ~tens of µm resolution |
Both routes run here, so the recommendation follows your geometry, not our tooling: UBM, AuSn, indium, and gold by lift-off; Cu, thick solder, and tall gold via electroplating.
the resist-free route
Some devices cannot meet a resist or a solvent at all. For them, the pattern comes from a stencil instead of lithography, and it runs on the same evaporators.
How It Works
A silicon or molybdenum stencil is clamped to the wafer and metal evaporates through its openings, depositing only where the stencil allows. No resist is spun, no solvent ever touches the device, and there is no lift-off step to survive. Resolution is honest-but-modest: tens of microns, set by stencil thickness and the stencil-to-wafer gap, with softened edges where the gap allows spread.
Where It Earns Its Keep
Released MEMS structures that a spin coat would glue shut, organic and temperature-fragile device layers that solvents attack, and cryogenic parts where residue budgets are absolute. The original C4 bumps were shadow-masked for decades, so the heritage is real. We run it alongside the resist routes and recommend per program, stencil when resist is the risk, lift-off when resolution is.
Lift-off wins when the metal is thin, when the alloy composition must be set at deposition rather than by a bath, when no practical plating chemistry exists, or when interface purity decides the device. Plating wins on thickness, sidewall profile, throughput, and material cost. Shadow masks win when resist itself is unacceptable. Everything else is detail.
Metals available for lift-off patterning
All metals are deposited by PVD (sputtering or evaporation) depending on the material and target film properties. Stacks (e.g. Ti/Au, Ti/Pt, TiW/Au) are available for adhesion layer + functional metal in a single lift-off step.
| Metal / Stack | Deposition Method | Typical Thickness | Primary Applications |
|---|---|---|---|
| Ti/Au | Sputter (Ti) + sputter or e-beam evap (Au) | 10-50nm Ti / 50-500nm Au | Bond pads, electrodes, RF contacts, ohmic contacts |
| Ti/Pt | Sputter (Ti) + sputter (Pt) | 10-30nm Ti / 50-200nm Pt | Biomedical electrodes, MEA, neural probes, MEMS sensors |
| AuSn 80/20 | PVD multi-layer (Au/Sn stacked layers) | 1-5µm total stack | Eutectic bump definition for flip-chip, hermetic sealing |
| Ti/TiN | Reactive sputter | 20-100nm Ti / 50-200nm TiN | Diffusion barriers, UBM adhesion layers |
| Ni / NiCr | Sputter or e-beam evaporation | 50-500nm | Thin-film resistors, UBM, solderable surfaces |
| Al / AlCu | Sputter | 100nm-2µm | Interconnect metal, MEMS structural layers |
| TiW/Au | Sputter | 50nm TiW / 100-300nm Au | UBM for AuSn and SnAg solder, RDL seed layers |
Other metals and custom stacks available on request. Minimum feature size and maximum film thickness are interdependent - contact us with your specific requirements.
Where lift-off patterning is used
Biomedical Electrodes
Au and Pt microelectrode arrays (MEAs) for neural recording, retinal implants, and lab-on-chip biosensors are patterned by lift-off. The electrodes must be noble metal to resist corrosion in physiological fluids - wet etching is not viable for either material.
RF & MEMS Contacts
RF MEMS switches, SAW/BAW resonator contact pads, and ohmic contacts on GaAs and GaN devices use Au or Ti/Au lift-off metallization. The underlying III-V or piezoelectric substrate would be attacked by Au etchants, making lift-off the only compatible patterning approach.
AuSn Bump Definition
Wafer-level AuSn eutectic bumps for flip-chip bonding of laser diodes onto silicon photonic PICs, MEMS hermetic sealing, and RF MEMS packaging are defined by PVD lift-off. The exact Au:Sn ratio is set by the deposited layer thicknesses - something wet etch cannot preserve.
RDL & UBM Seed Layers
Under-bump metallization (UBM) and redistribution layer (RDL) seed layers are often defined by lift-off of Ti/Au or TiW/Au stacks before electroplating. Lift-off provides the fine pitch capability and clean edge definition needed for sub-50µm pitch UBM on advanced packaging wafers.
🟣 Flexible & metallic substrates: Liftoff patterning is also available on polyimide (PI) film and thin SUS stainless steel substrates for flexible sensor and thin-film thermocouple fabrication.
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