At Nanosystems JP Inc., we offer a comprehensive wafer bonding capability covering eight bonding techniques. From room-temperature hybrid bonding with ±1µm Cu-Cu alignment, to eutectic hermetic seals below 300°C, to ultra-high vacuum SAB for LiNbO₃-Si heterogeneous integration. Chips to 12-inch wafers. C-SAM inspection on every bond.
Most foundries offer 2–3 bonding methods. We offer all eight, from high-precision hybrid bonding for 3D-IC to hermetic anodic bonding for MEMS packaging. Your device may need more than one technique; we coordinate the full bonding sequence .
These methods use a deposited or applied intermediate layer, metal, eutectic alloy, glass, or polymer, to create the bond. The intermediate layer determines bonding temperature, mechanical strength, hermeticity, and electrical conductivity.
The leading technique for face-to-face 3D-IC stacking. Combines direct dielectric fusion bonding (SiO₂-to-SiO₂) and Cu-Cu metal diffusion bonding in one integrated process. Both surfaces are CMP-planarised to <0.5nm Ra, plasma-activated, pre-bonded at room temperature under atmospheric pressure (dielectric layers bond via van der Waals), then annealed at 100–300°C to drive Cu diffusion and form a solid Cu-Cu joint. Result: electrical connection and hermetic dielectric bond in a single step with ±1µm die-to-wafer alignment accuracy.
Also known as thermocompression bonding. Two metal surfaces, Al-Al, Cu-Cu, or Au-Au, are brought together under heat and mechanical compression. Metal atoms diffuse across the interface, creating a metallurgical joint that is both mechanically strong and electrically conductive in one step. No intermediate solder layer is required. The joint quality is verified by cross-section metallographic analysis. Used in hermetic MEMS packaging, optical module assembly, and 3D-IC bonding where solder reflow would introduce too much movement.
An intermediate eutectic alloy layer melts at a temperature lower than either constituent metal alone, enabling hermetic bonding below 300°C (well within CMOS back-end temperature limits). Available eutectic systems: AuSn (melts at ~278°C, 80Au:20Sn), AuGe (~361°C), AuSi (~363°C), AlGe (~419°C). The eutectic alloy is deposited by sputtering with adhesion layers (Ti or Cr) and diffusion barriers (Ni or Pt). Pre-treatment removes surface oxide by wet or dry etching before bonding. Produces true hermetic seals for MEMS gyroscopes, accelerometers, and RF MEMS switches.
A specially formulated glass paste (glass frit) is applied to one wafer surface by spin coating or screen printing, then heated to compact the frit into a dense glass layer, and finally bonded under thermo-compression at approximately 400°C. The glass frit composition is engineered to match the coefficient of thermal expansion (CTE) of the bonded materials, critical for preventing crack initiation during temperature cycling. Bonds glass-to-metal, glass-to-ceramic, and glass-to-silicon. Primary application: hermetic MEMS package lids on pressure sensors, gyroscopes, and MEMS resonators.
Polymer adhesive bonding at the lowest process temperatures, well below 200°C, using thermally or UV-curable adhesives. Available adhesives: polyimide (PI), epoxy, and BCB (benzocyclobutene). Permanent bonding for the final device, or temporary bonding using releasable adhesive films for carrier wafer attachment during thinning operations. BCB offers particularly low dielectric constant and excellent planarization for applications where the polymer layer must also serve as an interlayer dielectric. The most flexible and lowest-cost bonding technique, compatible with any completed CMOS wafer without thermal damage.
Three techniques bond wafer surfaces directly, no intermediate material. Fusion bonding, surface-activated bonding (SAB), and anodic bonding each use different physics to achieve permanent bonds at the wafer level.
Hydrophilic silicon wafer surfaces are bonded at room temperature by van der Waals forces after rigorous CMP cleaning and surface activation. The pre-bond interface contains water molecules and Si-OH groups that later condense during annealing (100–300°C) to form permanent covalent Si-O-Si bonds across the interface, the same bond strength as bulk silicon. Plasma-activated fusion bonding uses O₂ or N₂ plasma to increase surface hydroxyl density and reduce the required annealing temperature. Pre-bonding surface roughness must be <0.5nm Ra, confirmed by AFM before bonding. Bubble-free bond verified by IR transmission imaging.
In ultra-high vacuum (UHV), the wafer surface is bombarded by a Fast Atomic Beam (FAB), removing the native oxide and contamination layer without heating. The activated surface bonds to another activated surface at room temperature with covalent bond strength, no annealing required. This enables bonding of dissimilar materials that would delaminate during annealing due to CTE mismatch: LiNbO₃ wafer to Si (for optical modulators and SAW-MEMS hybrid filters), metals to ceramics, and compound semiconductors to Si. Maximum applied load: 100kN. Available for wafers and individual chips.
An electric field is applied across a borosilicate glass (sodium-containing) wafer bonded against silicon or metal at 250–450°C. The electric field drives Na⁺ ions away from the glass-silicon interface, creating a depletion region. Oxygen ions at the interface then migrate into the silicon, forming permanent Si-O bonds, a true hermetic seal without any intermediate material. The bonded structure can be glass-Si, glass-Si-glass (triple stack), or glass-metal. Alignment by IR-transparent imaging through the glass. Chip-scale to full 12-inch wafers. Primary applications: MEMS pressure sensors, gyroscopes, microfluidic chips, and photonics hermetic packaging.
A bond that looks good on the outside may contain internal voids, delaminations, and unbonded regions invisible to optical inspection. C-SAM (scanning acoustic microscopy) maps the entire bond interface acoustically before the wafer proceeds to any subsequent processing.
Every bonded wafer pair is scanned by C-SAM before proceeding. The acoustic map shows void density, unbonded edge regions, and delamination zones, quantified as a bond yield percentage. This data is included in the process report delivered to the customer.
| Technique | Temperature | Hermeticity | Electrical | Alignment | Primary Application |
|---|---|---|---|---|---|
| Hybrid Bonding | 100–300°C | Yes (dielectric) | Yes (Cu-Cu) | ±1µm | 3D-IC HBM stacking, logic-on-memory |
| Metal Diffusion (Al-Al) | 350–450°C | Partial | Yes | ±2µm | MEMS hermetic lid, thermocompression |
| Metal Diffusion (Cu-Cu) | 250–400°C | Partial | Yes | ±2µm | 3D-IC via bonding |
| Metal Diffusion (Au-Au) | 200–350°C | Partial | Yes | ±2µm | RF MEMS, optical module die attach |
| Eutectic, AuSn | <280°C | True hermetic | Yes | ±3µm | RF MEMS, VCSEL packaging, SiPho |
| Eutectic, AuGe | <361°C | True hermetic | Yes | ±3µm | Infrared detector packaging |
| Eutectic, AlGe | <420°C | True hermetic | Yes | ±3µm | MEMS sensor hermetic enclosure |
| Glass Frit | ~400°C | True hermetic | No | ±5µm | MEMS package lids, pressure sensors |
| Adhesive, PI / BCB | <250°C | No | No | ±3µm | Temporary carrier, flexible integration |
| Fusion Bonding | RT → 100–300°C | Yes | No | ±1µm | SOI, pre-TSV bonding, MEMS cap |
| SAB (Ultra-high vacuum) | Room temp | Yes | No | ±2µm | LiNbO₃-Si, dissimilar material bonding |
| Anodic Bonding | 250–450°C | True hermetic | No | IR align | MEMS sensors, microfluidics |
Hybrid bonding for high-bandwidth memory stacking, logic die bonded face-to-face to DRAM layer at ±1µm Cu-Cu precision. Each HBM stack (4–12 layers) requires multiple hybrid bonds. The dominant technique for AI accelerator and HPC memory bandwidth scaling.
Anodic and glass frit bonding for hermetically sealed MEMS gyroscopes, accelerometers, and pressure sensors. The hermetic cavity maintains vacuum or inert atmosphere, critical for long-term resonator Q-factor and sensor stability. Automotive and aerospace reliability standards.
Fusion and adhesive bonding of III-V compound semiconductor laser dies (InP, GaAs) to silicon photonic waveguide chips. SAB for LiNbO₃ modulator substrate bonding to Si. Low-temperature techniques prevent thermal degradation of waveguide coupling efficiency.
Eutectic AuSn bonding for hermetic flip-chip packaging of RF MEMS switches and SAW/BAW resonator chips. AuSn bonding temperature below 280°C preserves the piezoelectric properties of LiNbO₃ and LiTaO₃ filter substrates. Used in 5G front-end modules.
Anodic bonding seals glass-Si-glass microfluidic chips for DNA sequencing flow cells, electrophoresis chips, and point-of-care diagnostic devices. PDMS adhesive bonding for lab-on-chip research devices. Glass-Si hybrid chips with TSV electrical feedthroughs.
Thermocompression Au-Au die attach for SiC MOSFET and GaN transistor power modules requiring high-temperature operational stability. Glass frit bonding for ceramic-to-metal package sealing. Applied to automotive inverter modules and industrial power converters.
Fusion bonding of backside-illuminated (BSI) image sensor pixel wafer to CMOS readout wafer. Pre-bonding CMP achieves the surface flatness needed for large-area void-free bonding. Critical for consumer camera, scientific, and surveillance imaging sensors.
Eutectic or adhesive bonding for optical MEMS devices, MEMS mirrors for LIDAR beam steering, tunable Fabry-Pérot filters, and micro-spectrometers. Low-outgassing adhesive bonding maintains vacuum in optically sensitive cavities.
Fusion bonding of Si to oxidised Si handle wafer, the basis of Silicon-on-Insulator (SOI) substrate fabrication. Also: bonding of piezoelectric layers (LiNbO₃, LiTaO₃) to Si for RF filter engineered substrate manufacturing (RF-SOI and BAW filter templates).
Hybrid, metal diffusion, eutectic, glass frit, adhesive, fusion, SAB, and anodic, the complete toolkit. Your device stack may need hybrid bonding for 3D-IC plus anodic bonding for the MEMS cap, both done without splitting the project between vendors.
±1µm Cu-Cu + SiO₂ hybrid bonding available from 1-wafer prototypes, not only for high-volume production lots. Pre-bonding CMP to <0.5nm Ra is integrated in the same project. No separate planarization vendor to coordinate.
Ultra-high vacuum surface-activated bonding for LiNbO₃-on-Si, enabling next-generation optical modulator and RF filter substrates. Available at fewer than a dozen facilities worldwide. The CTE mismatch between LiNbO₃ and Si makes this impossible with conventional fusion bonding.
Pre-bonding CMP to achieve <0.5nm Ra surface roughness for fusion and hybrid bonding is coordinated . The most common failure in multi-vendor flows is surface degradation during wafer transfer between CMP and bonding steps, eliminated here.
Every bonded wafer is scanned by Scanning Acoustic Microscopy before proceeding. Bond yield map provided to the customer. Voids detected before dicing, not discovered at final test after all subsequent processing has been completed on a defective wafer.
Bonding available from individual chips (chip-to-wafer hybrid bonding for known-good-die stacking) to full 12-inch wafer-to-wafer. Useful when two dies being bonded are fabricated on different wafer sizes, common in heterogeneous photonic integration.
Several bonding techniques available at Nanosystems JP Inc. are used to form hermetic seals in device packaging - protecting sensitive MEMS structures from atmospheric exposure over the device lifetime. The appropriate technique depends on process temperature constraints, substrate materials, and the required degree of isolation.
A widely used route for MEMS hermetic encapsulation. A borosilicate or fused silica glass cap wafer is bonded directly to a silicon device wafer at moderate temperature using an applied electric field. The bond forms at the glass-silicon interface without an intermediate layer, leaving the device cavity clean. Suitable for inertial sensors, resonators, and pressure sensors.
A patterned glass frit paste is screen-printed or dispensed as a seal ring on the cap wafer, then reflowed during bonding. The technique tolerates surface topography variations better than direct bonding and is compatible with pre-released MEMS structures. Fused silica cap wafers with TGV feedthroughs can be integrated into glass frit bonding flows.
Metal eutectic bonding (AuSn, AuGe) provides a robust hermetic seal at relatively low process temperatures. The approach is used for compound semiconductor device packages, optoelectronic components, and applications requiring a metal seal ring around the device cavity.
For devices requiring both hermetic sealing and electrical feedthroughs through the glass cap, we coordinate TGV formation in fused silica or borosilicate glass with subsequent wafer-level bonding. Fused silica caps offer the additional benefit of optical transparency (UV to IR), making them suitable for optical sensor packages where light must pass through the cap layer. The complete sequence - substrate supply, via drilling, and bonding - is managed under one project at Nanosystems JP Inc.
Hybrid bonding is one step in a complete AI & HPC interposer packaging flow - TSV, TGV, RDL, and bonding all managed as one project at Nanosystems JP Inc.
🧪 Pre-bond surface cleaning: SC1, RCA, and piranha wet chemical cleaning can be coordinated as a pre-bond preparation step - critical for direct bonding, fusion bonding, and anodic bonding where surface cleanliness directly affects bond strength and void density.
Cleaning services →Share your process requirements, substrate, and production volume, A Nanosystems JP Inc. engineer will respond within 1 business day. Full quote typically within 7–10 business days, subject to project complexity and NDA requirements.