Core Semiconductor Processes : Step 10 of 11

CMP & Wafer
Grinding

At Nanosystems JP Inc., we offer chemical mechanical polishing for metals, insulators, and polymers, up to 12-inch wafers. Custom slurries for Cu damascene, Si, and SiC. Pre-bonding CMP for fusion and hybrid bonding. Optical grade polishing. Wafer thinning to 50µm for TSV reveal and 3D packaging. Compound semiconductor grinding: SiC, GaN, InP, GaAs, LiTaO₃.

CMP metals · insulators · polymerCustom Cu/Si/SiC slurriesPre-bonding CMPOptical grade polishingWafer thinning to 50µmTSV backside grindingSiC · GaN · InP · GaAsLiTaO₃ · Sapphire
50µm
Min wafer thickness after grinding
12″
Max wafer size for CMP
Custom
Slurry formulations
SiC/InP/GaAs
Compound semi grinding
CMP, Chemical Mechanical Polishing
Planarization for metals, insulators, and polymers

CMP combines chemical etching and mechanical abrasion to create atomically flat surfaces, essential for multi-layer device fabrication where surface topography must be controlled to within nanometres.

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Metal CMP

Copper damascene CMP removes overburden Cu and stops precisely on the barrier layer, the key step in BEOL interconnect and RDL fabrication. Also: Al, W, Ta, and TiN planarization for MEMS electrodes, contact metals, and gate electrodes. Endpoint detection by eddy current (on Cu) or optical reflectometry prevents over-polish into the barrier layer. Cu dishing within wide lines and SiO₂ erosion between closely spaced lines are measured and reported post-CMP.

Cu damasceneAl · W · Ta · TiNEddy current endpointCu dishing measuredBEOL · RDL
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Insulator CMP (SiO₂/SiN)

Oxide and nitride planarization for shallow trench isolation (STI) fill, pre-bonding surface preparation, and interlayer dielectric (ILD) planarization between metal layers. Excellent within-wafer uniformity across 12-inch substrates. Low defectivity slurry chemistries minimize scratch density on STI oxide, critical for maintaining gate oxide integrity adjacent to STI edges.

SiO₂ · SiNSTI fill planarizationILD planarizationPre-bonding surface prep12 inch wafer
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Polymer CMP (Polyimide/BCB)

CMP of polyimide, BCB, and other organic dielectric layers used in RDL fabrication and advanced packaging. Planarises polymer passivation layers after cure and patterning to enable subsequent Cu metallisation and lithography. BCB CMP is particularly critical for fan-out FOWLP where multi-layer polymer RDL requires each layer to be perfectly flat before the next layer is coated.

Polyimide · BCBRDL planarizationFan-out FOWLPPolymer passivationAdvanced packaging
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Pre-Bonding CMP

Ultra-precise CMP immediately before wafer bonding, achieving <0.5nm Ra surface roughness required for direct fusion bonding (Si-Si) and Cu-Cu hybrid bonding. Surface roughness and flatness are verified by AFM before the wafer pair proceeds to bonding. Even a single surface particle or scratch can create a void in the bond interface that propagates during annealing, pre-bonding CMP is the most defect-sensitive CMP application we perform.

<0.5nm Ra targetAFM verifiedFusion bonding prepHybrid bonding prepZero tolerance for particles
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Optical Grade Polishing

Sub-Ångström surface polishing for fused silica, quartz, sapphire, and calcium fluoride optical substrates. Required for high-power laser optics, UV photomask substrates, and precision mirror blanks where any surface micro-roughness increases scatter loss and reduces laser damage threshold. Polishing slurry, pad conditioning, and process parameters are different from semiconductor CMP, this is precision optics grinding, not standard semiconductor polishing.

Sub-Å RaFused silica · QuartzSapphire · CaF₂High-power laser opticsUV photomask substrates
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Custom Slurry Formulations

Custom CMP slurry formulations are available for non-standard applications: SiC polishing slurry for power device wafer preparation (SiC is among the hardest semiconductor materials, standard Si slurries do not work), Si wafer mirror polishing slurry, and custom oxide slurries for specific ILD materials. Custom slurry development typically requires 2–4 weeks of process qualification on monitor wafers before production use.

SiC custom slurrySi mirror polish slurryCustom ILD slurry2–4 week qualificationSiC power devices
Wafer Grinding & Thinning
From 4-inch to 12-inch, down to 50µm

Wafer thinning by backside grinding is essential for TSV reveal, 3D packaging, and reducing thermal resistance in power devices.

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Standard Si Wafer Thinning

Backside grinding of silicon wafers from 4 inches to 12 inches using infeed grinding for stable, controlled thickness. Target thickness down to 50µm for TSV Cu tip exposure and 3D-IC stacking; prototype runs to 20µm on request. Coarse diamond grinding removes bulk material; fine-mesh wheel finishing then reduces the sub-surface damage layer, improving die flexural strength without requiring a full CMP stress-relief step. A subsequent dry-polish or CMP step is also available where flatness requirements demand it. Thickness uniformity ±2µm within-wafer. Thickness map provided post-grind. Carrier wafer bonding available for wafers thinned below 150µm. Singulated chip thinning also available on request.

4–12 inchDown to 50µm±2µm uniformityFine-mesh wheel finishStress relief after grindCarrier wafer supportSingulated chip thinning
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Protective Tape Lamination & Removal

Backgrinding requires a protective tape on the device face to prevent surface damage during grinding. At Nanosystems JP Inc., we offer protective tape lamination before grinding and clean removal after - including UV-release tape for device-side adhesive that cannot withstand solvent exposure. Tape selection is matched to the wafer material, device topology, and subsequent process steps. This is included as part of the coordinated backgrinding service, not a separate job for the customer to manage.

Protective tape lamination UV-release tape available Post-grind tape removal Matched to wafer material 5–12 inch wafers
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Backside Grinding for TSV Reveal

Controlled thinning specifically targeting TSV Cu tip depth, grinding to within a few micrometres of the Cu tips from the backside. Combined with subsequent dry etch reveal, PECVD passivation, and CMP to complete the TSV reveal flow. Target thickness is calculated from the original TSV depth minus the desired Cu protrusion height. Coordinated directly with our TSV reveal service, both steps handled in one project.

TSV reveal prepTarget: TSV depth − protrusionCoordinated with reveal etchSame PM as TSV reveal3D-IC · Interposer
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Compound Semiconductor Grinding

Precision grinding of InP, GaAs, GaN-on-Si, and GaN-on-SiC wafers. Compound semiconductors have different mechanical properties than silicon, they are more brittle, have lower fracture toughness, and have preferential cleavage planes that cause chipping under standard Si grinding conditions. Dedicated grinding wheels and process parameters prevent edge chipping and surface cracking in these materials.

InP · GaAsGaN-on-Si · GaN-on-SiCDedicated grinding wheelsBrittle material handlingCleavage plane awareness

SiC Wafer Grinding

Silicon carbide is the hardest commonly processed semiconductor (Mohs hardness 9.5), requiring diamond grinding wheels and specialized process control. Post-grinding CMP with custom SiC slurry achieves the smooth low-RMS surface required for gate oxide growth on SiC MOSFETs. The combination of grinding + SiC CMP reduces the surface step-bunching and polishing scratches that degrade SiC gate oxide reliability.

4H-SiCDiamond grinding wheelsCustom SiC CMP slurryLow-RMS for gate oxideSiC MOSFET prep
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LiTaO₃ / LiNbO₃ Grinding

Lithium tantalate (LiTaO₃) and lithium niobate (LiNbO₃) grinding and polishing for SAW (Surface Acoustic Wave) filter substrates. Both materials are piezoelectric single crystals requiring careful process control to avoid cracking along cleavage planes during grinding. Polished to the crystal-face roughness specification required for SAW device performance (Ra <0.5nm for SAW frequency >2GHz).

LiTaO₃ · LiNbO₃SAW filter substratesRa <0.5nmCleavage plane control5G SAW/BAW filters
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Sapphire & Glass Grinding

Sapphire (Al₂O₃) grinding for LED substrate thinning, UV window thinning, and silicon-on-sapphire (SOS) substrate preparation. Glass substrate thinning and edge chamfering for large-format panel processing. Inspection by wafer surface analyzer (WSA) measures surface roughness, bow, and warp after grinding, results included in the lot process data sheet.

Sapphire · GlassLED substrate thinningSOS preparationWSA inspection includedLarge-format glass panels
Process Specifications
CMP and grinding parameters
ProcessEndpoint/MetrologyKey SpecificationApplication
Metal CMP (Cu)Eddy current endpointCu dishing ≤20nm (100µm line)Cu RDL, BEOL damascene, TSV CMP
Insulator CMP (SiO₂)Optical endpointWithin-wafer non-uniformity ≤5%STI, ILD, pre-bonding
Polymer CMP (PI/BCB)Time/thickness controlPlanarised to ≤5nm stepRDL passivation, FOWLP
Pre-bonding CMPAFM surface measurementRa ≤0.5nmFusion bonding, hybrid bonding
Optical grade polishingInterferometryRa ≤0.1nm (sub-Å)Laser optics, UV substrates
Si wafer thinningThickness gauge±2µm uniformity; down to 50µmTSV reveal, 3D-IC
SiC grinding + CMPWSA surface analyzerRa ≤0.3nm post-CMPSiC MOSFET gate oxide prep
Compound semi grindingThickness gauge + WSAChip-free, cleavage-safeInP, GaAs, GaN, LiTaO₃
Applications
CMP and grinding across power, packaging, and photonics
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3D-IC TSV Reveal

Backgrinding to 50µm approaches Cu TSV tips from the backside; CMP after reveal etch exposes clean Cu contacts. Our CMP and grinding are coordinated with TSV fabrication and reveal in the same project, no inter-vendor wafer transfers.

Backgrind 50µm → dry etch reveal → passivation CMP · TSV · 3D-IC

SiC Power Devices

SiC wafer grinding + custom SiC CMP slurry to achieve the low-RMS surface required for gate oxide growth. Carbon cap annealing combined with post-anneal CMP provides the lowest possible surface roughness on 4H-SiC for high-reliability MOSFET gate oxide.

Diamond grind → SiC custom CMP → gate oxide prep · SiC MOSFET · SBD
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Wafer Bonding Preparation

Pre-bonding CMP achieves <0.5nm Ra for fusion and hybrid bonding. Surface quality verified by AFM before bonding. The most common yield loss in wafer bonding is surface particle and roughness defects, our pre-bonding CMP eliminates both.

CMP <0.5nm Ra → AFM verify → bonding · Fusion · Hybrid bonding · 3D-IC
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SAW Filter Substrates

LiTaO₃ and LiNbO₃ grinding and polishing for 5G SAW and BAW filter production. Surface roughness Ra <0.5nm required for SAW frequency stability above 2GHz. Cleavage-plane-aware grinding prevents yield loss from crystal cracking.

LiTaO₃ · LiNbO₃ · Ra <0.5nm · SAW filters · 5G · RF front-end
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Silicon Photonics

Pre-bonding CMP for SOI wafer bonding, achieving the flatness needed for void-free direct bonding of silicon photonic device layer to handle wafer. Optical grade polishing for fused silica waveguide substrate preparation.

Pre-bonding CMP · SOI bonding · Fused silica polishing · SiPho substrate
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LED & Sapphire Substrates

Sapphire substrate thinning for LED chip-scale packaging and sapphire-on-silicon sensor substrates. Post-epitaxy sapphire back-thinning for laser lift-off and GaN LED singulation by stealth laser dicing.

Sapphire thinning · LED CSP · Laser lift-off prep · GaN LED · SOS
Why Nanosystems JP Inc.
CMP and grinding integrated with packaging and bonding
01

Custom SiC slurry expertise

SiC requires a specifically formulated abrasive slurry, not the same chemistry as silicon CMP. SiC polishing slurries specifically for power device substrate preparation are available.

02

Integrated TSV reveal flow

CMP, backgrinding, dry etch reveal, and passivation CMP for TSV reveal are coordinated as a single project. No wafer shipping between each sub-step of the reveal flow.

03

Compound semiconductor specialist

InP, GaAs, GaN, LiTaO₃, and SiC each require different grinding wheels, feed rates, and subsequent CMP recipes. We process all these routinely alongside standard silicon.

04

Pre-bonding CMP for direct bonding

Our pre-bonding CMP achieves the flatness and cleanliness required for direct fusion bonding and Cu-Cu hybrid bonding, verified by AFM before the wafer advances to bonding.

05

Optical grade available

Sub-Ångström polishing for laser optics and UV substrates, requiring completely different process control from standard semiconductor CMP.

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Surface analyzer QC included

Post-grinding and post-CMP surface quality verified by WSA (wafer surface analyzer) before proceeding. Roughness, bow, and warp data included in process data sheet.

Next in your process flow

Dicing: After CMP and thinning, the wafer is singulated into individual dies by blade dicing, stealth laser dicing, or diamond scribing.

Dicing →

Start your project.
Response within 1 business day.

Share your process requirements, substrate, and production volume, A Nanosystems JP Inc. engineer will respond within 1 business day. Full quote typically within 7–10 business days, subject to project complexity and NDA requirements.

[email protected] · +81-3-5288-5569 · NDA available

All Services
Full process flow →
Substrates
🔷 Substrate & WafersSi, SiC, GaN, glass, sapphire 🔬 Fused Silica WafersQuartz · borosilicate · low CTE 🟣 PI Film & SUS Sensor FabRoll-to-roll · sensor patterning
Front-End
🎭 Mask FabricationGDS to chrome mask, DRC 💡 PhotolithographyE-beam 20nm to 500×600mm 🔬 NanoimprintingUV & thermal NIL 🔵 Thin Film DepositionPVD, CVD, ALD, MBE ⬆️ LiftoffMetal pattern · shadow mask ⚡ ElectroplatingCu TSV fill, DPC, LIGA ⚗️ EtchingICP-RIE, DRIE >50:1 🌡️ AnnealingN₂/H₂/vacuum/RTA 🎯 Ion ImplantationB/P/As/Al/N implant 🔶 CMP & GrindingCu CMP, 50µm thinning ✂️ DicingBlade, stealth laser 🧪 Wafer CleaningRCA, plasma, megasonic
Advanced Packaging
🔗 Wafer BondingHybrid, eutectic, fusion 📌 TSV FabricationHigh AR, void-free Cu fill 🔓 TSV RevealBackgrind → etch → CMP 🪟 TGV FabricationThrough-glass via 📐 RDL FabricationBCB/PBO/PI + damascene 📦 Packaging & AssemblyWire bond, flip-chip 📚 3D/2.5D PackagingTSV+RDL+UBM+C4 🥇 AuSn BumpPVD lift-off, fluxless 🧬 Biochip & MicrofluidicsGlass 500×600mm, NIL 🔆 SiPho PackagingTSV·RDL·UBM·C4 for PIC
Industries
🤖 AI & HPC PackagingCoWoS-style, 2.5D/3D 💎 Silicon PhotonicsSOI · AuSn · TSV interposer 🚗 AutomotiveMEMS sensors, SiC power 🧬 Life SciencesLab-on-chip, biosensors 🔭 All Industries → Request a Quote →
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⚙️ Capabilities Overview
Substrates
🔷 Substrate & WafersSi, SiC, GaN, glass, sapphire 🔬 Fused Silica WafersQuartz · borosilicate · low CTE 🟣 PI Film & SUS Sensor FabRoll-to-roll · sensor patterning
Front-End
🎭 Mask FabricationGDS to chrome mask, DRC 📷 PhotolithographyE-beam 20 nm to 500×600 mm 🔬 NanoimprintingUV & thermal NIL 🫧 Thin Film DepositionPVD, CVD, ALD, MBE ⬆️ LiftoffMetal pattern · shadow mask ⚡ ElectroplatingCu TSV fill, DPC, LIGA 🌊 EtchingICP-RIE, DRIE >50:1 🔥 AnnealingN₂ / H₂ / vacuum / RTA ⚛️ Ion ImplantationB / P / As / Al / N implant 🔄 CMP & GrindingCu CMP, 50 µm thinning 💎 DicingBlade, stealth laser 🧪 Wafer CleaningRCA, plasma, megasonic
Advanced Packaging
🔗 Wafer BondingHybrid, eutectic, fusion 📌 TSV FabricationHigh AR, void-free Cu fill 👁️ TSV RevealBackgrind → etch → CMP 🪟 TGV FabricationThrough-glass via 🔀 RDL FabricationBCB / PBO / PI + damascene 📦 Packaging & AssemblyWire bond, flip-chip 📚 3D / 2.5D PackagingTSV + RDL + UBM + C4 🥇 AuSn BumpPVD lift-off, fluxless 🧬 Biochip & MicrofluidicsGlass 500×600 mm, NIL 🔆 SiPho PackagingTSV · RDL · UBM · C4 for PIC
Industries
🤖 AI & HPC PackagingCoWoS-style, 2.5D / 3D 💡 Silicon PhotonicsSOI · AuSn · TSV interposer 🚗 AutomotiveMEMS sensors, SiC power 🧬 Life SciencesLab-on-chip, biosensors 🔭 All Industries → Request a Quote →