Core Semiconductor Processes : Step 7 of 11

Electroplating &
Electroforming

At Nanosystems JP Inc., we offer electroplating and electroless plating across all major semiconductor and compound substrates - Si, SiC, GaAs, InP, GaN, glass, sapphire, and AlN ceramic - covering bump formation, UBM, TSV/TGV void-free fill, LIGA electroforming, and DPC on ceramic. The metal menu spans Cu, Ni, Au, Ag, Pd, Rh, Ru, Pt, AuSn, SnAg, and Indium - including low-melting-point In for IR detector arrays and cryogenic assembly where conventional solder temperatures are not an option. Wafers 4–12 inch, ultra-thin handling to 60µm, prototypes from a single wafer.

Cu TSV/TGV void-free fillDPC on ceramicCu · Ni · Au · Ag · SnAuSn · SnAg · Pd · Rh · Ru · PtElectroless UBM - ENIG / ENEPIGLIGA electroforming Ni / Pd-Ni / Ni-Co1µm diameter structuresLarge panel support
300mm
Max wafer size
1µm
Min structure diameter
Void-free
Cu TSV/TGV fill
3D
LIGA metallic structures
Two Distinct Services
Electroplating for interconnects, electroforming for 3D microstructures

At Nanosystems JP Inc., we offer standard semiconductor electroplating for Cu/Ni/Au/AuSn interconnects and packaging, plus specialist LIGA electroforming for high-aspect-ratio 3D metallic structures in life sciences, optics, and filtration.

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Cu TSV / TGV Fill - Complete Void-Free

Complete, void-free copper filling of Through-Silicon Vias (TSV) and Through-Glass Vias (TGV) using superfill (bottom-up) additive electrolyte chemistry. Cu deposits from the via bottom upward, eliminating the voids that top-down fill produces in high-aspect-ratio geometries. Full fill is verified by cross-section SEM before CMP proceeds. Post-plating anneal at ~400°C for stress relief and grain stabilisation. For 3D-IC stacking, silicon and glass interposers, and MEMS-on-CMOS integration.

Superfill bottom-upVoid-free SEM verifiedTSV · TGVAnneal ~400°C N₂3D-IC · Interposer
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Conformal TSV / TGV Plating

Conformal (non-fill) Cu or Ni plating on TSV and TGV sidewalls, used as a diffusion barrier, RF shielding layer, or for coaxial via structures in RF MEMS and mmWave packaging. Unlike superfill plating which fills the via solid, conformal plating maintains the via opening while establishing electrical continuity on sidewalls. Applied in RF front-end modules and high-isolation millimetre-wave through-substrate interconnects.

Conformal sidewall platingRF coaxial viammWave shieldingTSV · TGVNon-fill, open via

DPC, Direct Plating Copper

DPC process enables copper deposition directly onto ceramic substrates, AlN, Al₂O₃, for power electronics packaging requiring high thermal conductivity substrate plus fine-pitch Cu circuit traces. Sputtered adhesion layer enables Cu electroplating on non-conductive ceramic surfaces. Used in SiC MOSFET and GaN transistor power modules where AlN substrate thermal conductivity (170 W/m·K) is essential for heat extraction.

AlN · Al₂O₃ ceramicSiC/GaN power modules170 W/m·K thermalFine-pitch Cu tracesPower electronics

Ni · Au · Ag · Pd · Rh · Ru · Pt · AuSn · In

Not every device takes the same surface finish. Au is the standard for wire-bondable and ACF-bondable pads. AuSn 80/20 eutectic is the choice for hermetic packages and laser-diode mounting where the joint must survive vacuum seal and high-temperature operation. Indium handles the cases where even AuSn is too hot - IR detector arrays, cryogenic circuits, photonic integration on temperature-sensitive compound substrates. Rh and Ru go onto MEMS switch contacts where Au would cold-weld. Pt onto sensor electrodes and implantable devices where chemical stability matters more than cost. Every stack uses a Ni diffusion barrier before any Au-family finish to prevent intermetallic growth over the device lifetime.

Ni · Au · AuSnRh · Ru · PtIn - low-temp bondingIn - IR detector flip-chipCryogenic device assemblyAuSn eutectic flip-chipBond pads · Hermetic packaging
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Electroless UBM - ENIG / ENEPIG

Wafers that cannot accept external current - active power devices, fragile thin-film structures, fully processed CMOS - still need a plated UBM to accept solder or wire bond. Electroless Ni/Au (ENIG) and Ni/Pd/Au (ENEPIG) deposit by chemical reaction alone, with no current path through the device. Ni provides the diffusion barrier; Au gives the solderable and wire-bondable surface. ENEPIG adds a Pd interlayer that improves joint reliability at elevated temperature, making it the preferred finish for SiC and GaN automotive power devices. AEC-Q compatible process flows available; thick-Ni and thick-Cu electroless variants on request.

ENIG Ni/Au ENEPIG Ni/Pd/Au SiC · GaN · IGBT No external current Power device UBM Wire bondable AEC-Q compatible
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SnAg Solder Bumping - Flip-Chip

SnAg 96.5/3.5 solder bumping for flip-chip assembly where the bonding temperature, hermetic requirement, and cost profile favour a conventional lead-free solder over AuSn. Bumps are formed electrolytically on the UBM, reflowed to sphere, and verified for coplanarity by profilometry before shipping. Pitch from 100µm, height 20–100µm, 4–12 inch wafers. Custom SnAg alloy ratios available for adjusted melt point or joint ductility - specify your reflow window and we will confirm the alloy and process conditions.

SnAg 96.5/3.5 Flip-chip bumping Pitch from 100µm 20–100µm bump height 4–12 inch wafers Post-plate reflow Lead-free · RoHS
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In · SnAg Combinations - Low-Temperature & Custom Alloy

Some assemblies cannot survive standard solder temperatures. Indium (In) melts at 156°C - well below the 220°C+ required by SnAg - making it the right choice when an active III-V device region, a detector material, or a cryogenic component sits immediately adjacent to the bond interface. We use In for IR focal plane array flip-chip (HgCdTe, InSb, InGaAs), quantum computing device packaging, and photonic chip co-integration where laser junctions would degrade under conventional reflow. Indium is also mechanically compliant, which matters when two dissimilar materials are being bonded and CTE mismatch would crack a stiffer solder joint. Stack options include Ni/In and Cu/Ni/In. SnAg alloy composition is available beyond 96.5/3.5 - enquire with your target melt point and we will specify the ratio.

In - 156°C bonding IR detector arrays HgCdTe · InSb · InGaAs Cryogenic devices Photonic co-packaging CTE mismatch compliance Cu/Ni/In · Ni/In stacks SnAg custom alloy ratio
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LIGA Electroforming, Ni

Electroforming into X-ray LIGA resist molds to create high-aspect-ratio nickel microstructures with diameter as small as 1µm. The LIGA mold (deep PMMA exposed by X-ray) defines the geometry; electroformed Ni fills the mold precisely. Applications: micropore membranes with controlled pore size, microneedle arrays for drug delivery, micro-mesh filters, nebulisers for aerosol generation, and NIL molds for nanoimprinting.

1µm min diameterHigh aspect ratioX-ray LIGA moldMicropore membranesMicroneedles · Filters
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LIGA Electroforming, Pd-Ni / Ni-Co

Palladium-nickel (Pd-Ni) and nickel-cobalt (Ni-Co) electroforming for enhanced hardness, wear resistance, and biocompatibility compared to pure Ni. Pd-Ni offers superior corrosion resistance and biocompatibility for life science microstructures in direct contact with biological samples. Ni-Co provides higher hardness for precision molds and mechanical components requiring long service life.

Pd-Ni · Ni-CoBiocompatibleHard · Wear resistantLife sciencesPrecision molds
Substrate Compatibility
Electroplating across all major semiconductor and compound substrates

The choice of plating process - electrolytic, electroless, or DPC - depends on the substrate conductivity, electrode material, and device sensitivity to current. At Nanosystems JP Inc., we work across all major wafer materials, accepting pure Al, AlSi, AlSiCu, and AlCu electrode formats, with the substrate coverage below.

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Silicon & SOI

Standard Si wafers 4–12 inch processed in electrolytic and electroless flows. Ultra-thin wafers handled to 60µm with adapted fixturing. SOI accepted for photonics-on-silicon and MEMS-on-CMOS integration. Al, AlSi, and AlSiCu electrode formats all accepted for electroless UBM without additional pre-treatment.

Si 4–12 inch Ultra-thin to 60µm SOI · FD-SOI Al / AlSi / AlSiCu electrodes

SiC & GaN-on-Si

SiC and GaN-on-Si power devices demand UBM that survives die-attach reflow, wire bonding, and operating temperatures above 175°C. We apply electroless Ni/Au and ENEPIG directly onto Al-based electrodes, with electroless thick Cu as an option for Cu wire bonding and Cu sintering applications in high-current SiC modules. AEC-Q process flows available.

SiC (4H, 6H) GaN-on-Si Electroless Ni/Au · ENEPIG Electroless thick Cu ≥5µm AEC-Q compatible
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III-V Compound Semiconductors

GaAs, InP, GaN, InGaAs, and related compound substrates for RF front-end, photonic integrated circuits, and imaging detectors. Electrolytic Au, AuSn, and SnAg bumping for standard flip-chip interconnect. For InSb, HgCdTe, and InGaAs infrared focal plane arrays, we offer Indium (In) bump plating - the only practical flip-chip metal at the sub-160°C bonding temperatures these detector materials require.

GaAs · InP InGaAs · InSb GaN · HgCdTe In bump - IR FPA Au · AuSn · SnAg
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Glass & Fused Silica

Glass substrates for optical MEMS, photonic packaging, and microfluidic chips - fused silica, borosilicate, and custom interposer glass. TGV copper void-free fill for 3D glass interposer packaging. Where full fill is not needed, conformal Cu or Ni on via sidewalls provides electrical continuity for RF isolation and coaxial-via structures.

Glass interposer TGV Cu fill Fused silica · Borosilicate Conformal TGV Ni/Cu 4–8 inch
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Ceramic: AlN & Al₂O₃

Power module substrates - AlN at 170 W/m·K and Al₂O₃ - processed by DPC, where a Ti/Cu sputtered adhesion layer turns the non-conductive ceramic into a platable surface. Fine-pitch Cu circuit traces are then electroplated directly. Used in SiC MOSFET and GaN power module packages where the ceramic substrate carries both the electrical circuit and the primary heat extraction path.

AlN - 170 W/m·K Al₂O₃ ceramic DPC Cu traces SiC · GaN power modules Ti/Cu sputtered seed
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Sapphire, Resin & Specialty

Sapphire for GaN-on-sapphire LED and RF devices. Polyimide and resin substrates for flexible hybrid electronics and panel-level packaging. Square substrates, singulated chips, and non-standard wafer formats accepted with adapted fixturing - contact us with your substrate and we will confirm compatibility before quoting.

Sapphire Resin · Polyimide Singulated chips Square substrates Enquire for specialty
LIGA Electroforming
3D metallic microstructures with 1µm features and 100:1 aspect ratio
LIGA (Lithographie, Galvanoformung, Abformung) combines X-ray lithography, electroforming, and molding to produce metallic 3D microstructures that UV lithography and standard machining cannot achieve. Deep PMMA resist (up to millimetre depth) is exposed through an X-ray mask with perfect vertical sidewalls, then electroformed in Ni, Pd-Ni, or Ni-Co to produce the metallic micropart.
Aspect ratios up to 100:1, not achievable by UV lithography
Vertical sidewalls, no taper from UV diffraction
Feature diameter as small as 1µm
Structure height from tens of microns to millimetres
Ni, Pd-Ni, Ni-Co electroformed materials
Micropore membranes with controlled pore uniformity
Microneedle arrays for transdermal drug delivery
NIL molds and masters, durable Ni for production volume
Micro-mesh filters for filtration and separation
Nebulisers for pharmaceutical aerosol generation
Security microstructures for anti-counterfeiting
Microfluidic components for lab-on-chip devices
Process Specifications
Electroplating and electroforming parameters
ProcessMethodKey SpecApplication
Cu TSV/TGV fillSuperfill electroplatingVoid-free, SEM verifiedAnneal ~400°C; 300mm wafer + large panel
DPC on ceramicCu electroplating on AlN/Al₂O₃Via sputtered seed layerSiC/GaN power module substrate
In (Indium)ElectrolyticPure In, 156°C melt, 5–30µm bumpsIR detector FPA, cryogenic, photonic co-pack
SnAg alloyElectrolytic96.5/3.5 std; custom ratio on inquiryFlip-chip, pitch from 100µm, 20–100µm height
Ni / Au / AuSnElectroless + electrolyticMEMS contacts, UBM, flip-chipENIG/ENEPIG, AuSn 80/20 eutectic
Cu/Ni/Au, Cu/Ni/SnAg, Cu/Ni/InElectrolytic stackCombination plating, pitch ≥3µm L/SMicrobumps, fine-line RDL wiring
Electroless thick CuElectroless≥5µm, Al electrode directCu wire bond, Cu sinter, high-current SiC
Conformal TSV/TGVCu or Ni conformal plateSidewall only, via remains openRF coaxial via, mmWave shielding
LIGA, NiElectroforming in PMMA moldDiameter ≥1µm, AR up to 100:1Micropores, microneedles, filters
LIGA, Pd-NiElectroforming in PMMA moldBiocompatible, corrosion resistantLife science, implantable devices
LIGA, Ni-CoElectroforming in PMMA moldHigh hardness, wear resistantPrecision molds, mechanical parts
Applications
Electroplating and electroforming across semiconductor and life sciences
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3D-IC & Advanced Packaging

Void-free Cu TSV fill for 3D stacking and 2.5D interposers. AuSn bumping for silicon photonics flip-chip. Ni/Au UBM for solder wetting. The core metallisation steps in advanced packaging flows , all coordinated with our TSV fabrication and RDL services.

TSV Cu fill · AuSn bump · ENIG/ENEPIG UBM · 3D-IC · 2.5D interposer
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Micropore Membranes

Nickel micropore membranes by LIGA electroforming with precise pore size from 1µm upward. Used for microfiltration of biological samples, cell sorting, emulsification of pharmaceutical droplets, and MEMS flow control valves. Pore uniformity across the membrane is controlled by the X-ray mask geometry.

LIGA Ni · 1µm pores · Microfiltration · Cell sorting · Emulsification
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Microneedle Arrays

Hollow and solid Ni or Pd-Ni microneedle arrays for transdermal drug delivery and interstitial fluid sampling. LIGA electroforming creates arrays with precisely controlled height, tip sharpness, and hollow channel diameter. Pd-Ni for biocompatible implant-grade microneedles.

LIGA Ni/Pd-Ni · Microneedles · Drug delivery · ISF sampling · Biocompatible
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NIL Mold Fabrication

Nickel electroformed masters and working molds from Si or polymer originals. Ni molds withstand thousands of imprint cycles, essential for volume production of nanoimprinted structures. Harder and more durable than the Si master, enabling high-volume NIL without mold replacement.

Ni electroformed from Si master · NIL mold · Volume production · Durable

Power Electronics (DPC)

Direct Plating Copper on AlN and Al₂O₃ ceramic substrates for IGBT, SiC MOSFET, and GaN power module packaging. Combines high thermal conductivity ceramic substrate with fine-pitch Cu circuit traces, replacing the DBC (Direct Bonded Copper) process for applications requiring tighter feature control.

DPC · AlN · Al₂O₃ · SiC MOSFET · GaN · Power module · Fine-pitch Cu
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RF Coaxial Through-Substrate

Conformal Cu plating in TGV for coaxial feedthrough structures in RF MEMS and mmWave packages. The central signal via is surrounded by a conformally plated ground sleeve, providing 20–40dB isolation between adjacent signal lines through the substrate. Applied in 5G/6G front-end modules and satellite communication chips.

Conformal TGV · RF coaxial · 5G/6G FEM · mmWave · 20–40dB isolation
Why Nanosystems JP Inc.
Ten plating metals, all substrates, LIGA electroforming - <
01

Cu TSV fill integrated with DRIE

We etch the via by DRIE, deposit the liner by PECVD, seed by sputtering, and fill by electroplating, , in sequence, without inter-vendor wafer transfers between steps.

02

LIGA electroforming specialist

X-ray LIGA electroforming with features to 1µm diameter in Ni, Pd-Ni, and Ni-Co. Fewer than a dozen facilities worldwide offer this capability for life science and precision optics applications.

03

DPC for power packaging

Direct Plating Copper on AlN/Al₂O₃ for power device packaging, available alongside standard wafer-level plating, serving both MEMS and power electronics customers from the same coordinated project.

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Biocompatible materials

Pd-Ni and Ni-Co electroforming with biocompatibility characterisation for life science and medical device applications. Implantable-grade microneedles and micropore membranes.

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300mm wafer + large panel

Electroplating on standard wafers up to 300mm and on large-format glass panels for TGV and panel-level packaging. one coordinated process flow for wafer and panel formats.

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From 1 wafer prototype

Prototype plating on a single wafer to verify fill quality, stress levels, and surface finish before committing to full production lots. Same process recipe scales without re-qualification.

Next in your process flow

Etching: After electroplating, etching defines the metal interconnect pattern, or the underlying via structures that electroplating fills.

Etching →

Start your project.
Response within 1 business day.

Share your process requirements, substrate, and production volume, A Nanosystems JP Inc. engineer will respond within 1 business day. Full quote typically within 7–10 business days, subject to project complexity and NDA requirements.

[email protected] · +81-3-5288-5569 · NDA available

All Services
Full process flow →
Substrates
🔷 Substrate & WafersSi, SiC, GaN, glass, sapphire 🔬 Fused Silica WafersQuartz · borosilicate · low CTE 🟣 PI Film & SUS Sensor FabRoll-to-roll · sensor patterning
Front-End
🎭 Mask FabricationGDS to chrome mask, DRC 💡 PhotolithographyE-beam 20nm to 500×600mm 🔬 NanoimprintingUV & thermal NIL 🔵 Thin Film DepositionPVD, CVD, ALD, MBE ⬆️ LiftoffMetal pattern · shadow mask ⚡ ElectroplatingCu TSV fill, DPC, LIGA ⚗️ EtchingICP-RIE, DRIE >50:1 🌡️ AnnealingN₂/H₂/vacuum/RTA 🎯 Ion ImplantationB/P/As/Al/N implant 🔶 CMP & GrindingCu CMP, 50µm thinning ✂️ DicingBlade, stealth laser 🧪 Wafer CleaningRCA, plasma, megasonic
Advanced Packaging
🔗 Wafer BondingHybrid, eutectic, fusion 📌 TSV FabricationHigh AR, void-free Cu fill 🔓 TSV RevealBackgrind → etch → CMP 🪟 TGV FabricationThrough-glass via 📐 RDL FabricationBCB/PBO/PI + damascene 📦 Packaging & AssemblyWire bond, flip-chip 📚 3D/2.5D PackagingTSV+RDL+UBM+C4 🥇 AuSn BumpPVD lift-off, fluxless 🧬 Biochip & MicrofluidicsGlass 500×600mm, NIL 🔆 SiPho PackagingTSV·RDL·UBM·C4 for PIC
Industries
🤖 AI & HPC PackagingCoWoS-style, 2.5D/3D 💎 Silicon PhotonicsSOI · AuSn · TSV interposer 🚗 AutomotiveMEMS sensors, SiC power 🧬 Life SciencesLab-on-chip, biosensors 🔭 All Industries → Request a Quote →
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Services & Industries
⚙️ Capabilities Overview
Substrates
🔷 Substrate & WafersSi, SiC, GaN, glass, sapphire 🔬 Fused Silica WafersQuartz · borosilicate · low CTE 🟣 PI Film & SUS Sensor FabRoll-to-roll · sensor patterning
Front-End
🎭 Mask FabricationGDS to chrome mask, DRC 📷 PhotolithographyE-beam 20 nm to 500×600 mm 🔬 NanoimprintingUV & thermal NIL 🫧 Thin Film DepositionPVD, CVD, ALD, MBE ⬆️ LiftoffMetal pattern · shadow mask ⚡ ElectroplatingCu TSV fill, DPC, LIGA 🌊 EtchingICP-RIE, DRIE >50:1 🔥 AnnealingN₂ / H₂ / vacuum / RTA ⚛️ Ion ImplantationB / P / As / Al / N implant 🔄 CMP & GrindingCu CMP, 50 µm thinning 💎 DicingBlade, stealth laser 🧪 Wafer CleaningRCA, plasma, megasonic
Advanced Packaging
🔗 Wafer BondingHybrid, eutectic, fusion 📌 TSV FabricationHigh AR, void-free Cu fill 👁️ TSV RevealBackgrind → etch → CMP 🪟 TGV FabricationThrough-glass via 🔀 RDL FabricationBCB / PBO / PI + damascene 📦 Packaging & AssemblyWire bond, flip-chip 📚 3D / 2.5D PackagingTSV + RDL + UBM + C4 🥇 AuSn BumpPVD lift-off, fluxless 🧬 Biochip & MicrofluidicsGlass 500×600 mm, NIL 🔆 SiPho PackagingTSV · RDL · UBM · C4 for PIC
Industries
🤖 AI & HPC PackagingCoWoS-style, 2.5D / 3D 💡 Silicon PhotonicsSOI · AuSn · TSV interposer 🚗 AutomotiveMEMS sensors, SiC power 🧬 Life SciencesLab-on-chip, biosensors 🔭 All Industries → Request a Quote →