At Nanosystems JP Inc., we offer ICP-RIE, DRIE, RIE, and wet etching: four methods covering every material, geometry, and depth requirement. From 20nm optical waveguide sidewalls to 50:1 aspect ratio DRIE for TSV fabrication.
Most devices require more than one etch method. Running ICP-RIE for waveguide definition and DRIE for membrane release on the same wafer is standard, we coordinate it all under one project.
The highest-performance dry etch method. ICP generates a high-density plasma separately from the substrate bias, allowing independent control of ion flux and ion energy. This gives exceptionally high selectivity, high etch rate, low substrate damage, and smooth sidewalls, essential for optical waveguides, compound semiconductor devices, and piezoelectric MEMS.
The gold standard for deep silicon etching. The Bosch process alternates between etch cycles (SF₆ plasma) and passivation cycles (C₄F₈ polymer deposition), building up protection on sidewalls between each etch step. The result: near-vertical 90° sidewalls to depths exceeding 100µm with aspect ratios up to 50:1, the foundation of TSV fabrication and MEMS.
The versatile workhorse of dry etching. RIE uses a capacitively-coupled plasma where the substrate sits on the powered electrode, giving good directionality at lower capital cost than ICP. Supports both isotropic and anisotropic profiles depending on process conditions. Widely used for dielectric patterning, metal electrode definition, resist ashing, and surface cleaning.
Wet etching remains indispensable for high-throughput silicon bulk micromachining, oxide removal, and selective metal etching. KOH and TMAH exploit the crystallographic anisotropy of silicon to produce precise V-grooves, pyramidal pits, and membranes, widely used for pressure sensors and optical fibre alignment structures. BOE provides controlled oxide removal with excellent selectivity over silicon.
Understanding the physics behind each method helps select the right process for your device. These simplified cross-sections show what's happening at the wafer surface during each etch type.
Each etch method produces a different profile. Selecting the wrong method means re-spin, choosing correctly at the start saves weeks.
Our four etch methods cover virtually every material used in MEMS, semiconductor, and advanced packaging fabrication. Below is our process compatibility matrix drawn from our live capabilities.
| Material Category | Specific Materials | Recommended Method | Applications |
|---|---|---|---|
| Silicon | Si (bulk)Poly-Sia-SiSOI |
DRIE (deep)RIE (thin)KOH/TMAH (wet) |
TSV, MEMS structures, membranes, gates |
| Compound Semiconductors | GaAsAlGaAsInPGaNInGaAsAlN |
ICP-RIE |
VCSELs, LEDs, lasers, HEMTs, photodetectors, RF devices |
| Wide Bandgap / Power | SiCGaN-on-SiGaN-on-SiC |
ICP-RIE |
SiC MOSFETs, GaN HEMTs, power devices, Schottky diodes |
| Optical / Dielectrics | SiO₂SiNQuartzOxynitride |
ICP-RIE (waveguide)RIE (field)BOE (wet) |
Waveguides, ring resonators, cladding etch, via opening, isolation |
| Piezoelectric | PZTAlNLiNbO₃KNN |
ICP-RIE |
MEMS transducers, acoustic resonators, BAW filters, energy harvesters |
| Metal Electrodes | PtAuAlTiCrITONiCu |
RIE (Pt/Al)Wet etchants (Au/Cr/Ti) |
MEMS electrodes, BEOL interconnects, contact pads, sensor electrodes |
| DLC / Carbon films | DLCa-C:H |
RIE (O₂ plasma) |
Hard coatings, tribological films, MEMS wear layers |
| Resist / Polymer | PhotoresistSU-8Polyimide |
RIE (ashing)O₂ plasma |
Post-process resist strip, descum, surface activation, polymer pattern |
Our etching capability spans photonics, power electronics, MEMS, compound semiconductors, and advanced packaging, often within a single multi-process project.
ICP-RIE defines Si rib and ridge waveguides, ring resonators, and grating couplers with sub-nm sidewall roughness. Smooth sidewalls are non-negotiable for low-propagation-loss waveguides.
GaAs/AlGaAs mesa isolation, InP-based laser facet etching, GaN LED chip isolation. ICP-RIE provides the vertical profiles and smooth surfaces essential for optical performance.
SiC MOSFET trench gate etching, p-well and n+ source mesas, GaN HEMT isolation etching. ICP-RIE handles the chemical inertness of SiC that makes wet etching impractical.
AlN and PZT etch for BAW resonators and bulk acoustic wave filters. DRIE for silicon substrate removal and membrane release. RF MEMS switch fabrication.
DRIE Bosch process for Through-Silicon Via etching: 50:1 aspect ratio, >100µm depth, SiO₂ hard mask, near-vertical 90° sidewalls ready for oxide liner and Cu plating.
Pressure sensor membranes (DRIE or KOH), MEMS accelerometer proof masses (DRIE), gyroscope resonators, capacitive sensors, microfluidic channels.
DRIE for high-aspect-ratio microfluidic channels in silicon, KOH for V-groove fibre alignment, RIE for polymer and SiO₂ features on glass biochip substrates.
DRIE for CMUT membrane release, back-cavity etching for microphone diaphragms, PMUT fabrication with precise AlN film etch by ICP-RIE.
Sub-100nm features via ICP-RIE after e-beam lithography, nanopillars, gratings, photonic crystal cavities, anti-reflection structures for VR/AR optics.
Every etching project at Nanosystems JP Inc. is integrated with the preceding lithography and following deposition or CMP steps. We review your full process flow, not just the etch requirements.
We review your mask layout, substrate type, and film stack before quoting. This catches potential selectivity issues and allows us to recommend the optimal hard mask material.
Pattern definition . For deep DRIE we typically use SiO₂ hard masks for selectivity; for ICP-RIE on compound semiconductors we optimize resist thickness and bake conditions.
ICP-RIE, DRIE, RIE, or wet etching, or a combination. Process parameters are set per your target depth, profile, and selectivity requirements. Endpoint detection where required.
Post-etch SEM or profilometer measurement confirms etch depth, sidewall angle, and critical dimensions. We report results before proceeding to the next step.
Ashing, deposition, CMP, or bonding, the next step in your process flow proceeds without changing foundry. No coordination overhead between vendors.
A 50:1 aspect ratio means a trench 10µm wide can be etched to 350µm deep with near-vertical sidewalls. This is what makes deep TSV fabrication and through-wafer MEMS possible without substrate thinning.
Most etching-only vendors can run one method. We run all four, and integrate them with your lithography, deposition, and CMP in a single project.
ICP-RIE, DRIE, RIE, and wet etching managed as one project. No shipping wafers between vendors. No risk of contamination, handling damage, or mis-communication between process steps.
GaAs, AlGaAs, InP, GaN, InGaAs, and SiC, etched by ICP-RIE with optimized chemistries for each material system. Not a capability most MEMS-only foundries offer.
No minimum lot size for prototyping. Iterate on your etch recipe without committing to 25-wafer lots. Scale to production on the same process flow, no technology transfer needed.
We measure after etching, depth, CD, sidewall angle. If a parameter is out of specification, we tell you before proceeding. No surprises at the end of a 4-week run.
Your device architecture, mask layouts, and process parameters can be protected under NDA before anything is shared - just request one in your first message. Tokyo-based operations under Japanese IP law.
Full English technical documentation, quotations, and project updates. International customers, from Europe, North America, and across Asia, work with us directly without a Japanese intermediary.
Share your process requirements, substrate, and production volume, A Nanosystems JP Inc. engineer will respond within 1 business day. Full quote typically within 7–10 business days, subject to project complexity and NDA requirements.