At Nanosystems JP Inc., we offer precision doping for SiC MOSFETs, GaN HEMTs, IGBTs, Ga₂O₃ power devices, and advanced MEMS. Implant energies from 5 keV to 8 MeV, high-temperature implantation to 600°C, 60+ dopant species, pre-implant simulations, and rapid thermal annealing to 1800°C, all in one integrated flow.
Our ion implantation service is built around power device requirements, particularly the demanding needs of SiC and GaN, where standard room-temperature implantation is insufficient for proper crystal activation.
SiC and GaN require elevated substrate temperatures during implantation to prevent amorphisation and preserve crystal structure. We offer substrate heating to 600°C, essential for SiC MOSFET well implants and GaN HEMT isolation.
Over 60 dopant species available, covering all major n-type, p-type, and co-implant requirements across Si, SiC, GaN, GaAs, and Ga₂O₃. Rare species including Ca, Ba, La, Fe, Cr, and Sn available for advanced research and specialized device structures. Enquire for species not listed.
From small chips and 2-inch research samples to full 300mm production wafers. Handles all standard semiconductor substrates including Si, SiC, GaN, GaAs, InP, Ga₂O₃, sapphire, and glass. Tilt angles from 0° to 60° for channelling suppression or controlled channelling implants.
Post-implant activation annealing to 1800°C under Ar and N₂ atmospheres. Essential for activating Al, N, and B dopants in SiC, the highest-temperature step in power device fabrication.
SRIM/TRIM or TCAD simulations before every implant run. We model dopant distribution, peak concentration, straggle, and damage profiles to confirm your doping requirements are achievable before any wafers are processed.
Carbon cap deposition before high-temperature annealing prevents silicon evaporation and step bunching from SiC surfaces. Essential for maintaining sub-nm surface roughness (low RMS) after 1400°C+ anneals.
High-energy hydrogen implantation for layer separation (Smart Cut™-type processes), hydrogen-induced defect engineering, and high-concentration H for direct wafer bonding and SOI preparation. High-energy H⁺ isolation implant also used for VCSEL current aperture definition in photonic device fabrication.
Process parameters optimized specifically for power semiconductor device fabrication, not standard CMOS profiles. Our engineers understand the unique electrical requirements of blocking junctions, channel implants, and ohmic contacts in SiC and GaN.
Electrical and physical verification after implantation, available as part of the service flow. Four-point probe sheet resistance measurement confirms implanted dose uniformity across the wafer. Particle inspection and surface contamination checks included. SIMS depth profiling for dopant distribution confirmation on request. Process data reported with every lot before wafer release.
From standard n-type and p-type dopants for silicon to specialized implants for SiC activation and compound semiconductor isolation, all available. Enquire for additional species.
Color coding: ■ Key power device dopants ■ Compound semiconductor dopants ■ Standard & specialty
Ion implantation for SiC and GaN devices requires fundamentally different process parameters than standard CMOS. Our flows are tuned for the high-temperature requirements and precise doping profiles these devices demand.
SiC MOSFETs require multiple implant steps at elevated temperatures because room-temperature implantation creates amorphous damage layers that cannot be recovered by annealing. Hot implantation (400–600°C) maintains crystallinity through each step.
High-temperature implantation (600°C) + carbon cap + 1800°C RTA in one coordinated flow, not available as a piecemeal service elsewhere.
GaN HEMT fabrication uses ion implantation primarily for device isolation, a fluorine or nitrogen implant converts conducting GaN into semi-insulating material, defining the active device area without mesa etching (which improves device reliability).
Implant isolation eliminates the reliability issues of dry-etched mesa sidewalls, a best-practice approach for high-voltage GaN power devices.
Standard and power silicon device implantation flows, p-well, n-well, n+ emitter, p+ collector implants for IGBT structures. Also: base and emitter implants for bipolar transistors, LDMOS source/drain/body, and deep n-well for CMOS isolation.
Every implant run at Nanosystems JP Inc. is preceded by a detailed simulation of the doping profile. This catches problems before wafers are processed, saving time and cost on expensive SiC and GaN substrates.
The activation anneal is the final, and most demanding, step in the power device implant flow. We provide integrated RTA so your implanted wafers never leave the cleanroom between implant and anneal.
| Parameter | Specification | Notes |
|---|---|---|
| Wafer sizes | Chips & small pieces to 300mm wafers | Non-standard sizes on request |
| Substrate materials | Si, SiC, GaN, GaAs, InP, Ga₂O₃, Sapphire, Glass, InGaAs | All standard semiconductor substrates including ultra-wide bandgap |
| Implant temperature | Room temperature to 600°C (hot implantation) | 600°C required for SiC/GaN to prevent amorphisation |
| Dopant species | N, H, O, P, C, As, Ge, Al, Mg, Si, In, Ca, Ba, He, La, Sn, Cl, B, Ga, Fe, Cr + more | 60+ species available; enquire for others |
| Dose range | 1×10¹⁰ to 1×10¹⁷ cm⁻² | Multiple energies for box profiles; high-dose ohmic and threshold adjust both supported |
| Energy range | 5 keV – 8 MeV | Medium current: 5–700 keV; high energy: up to 8 MeV (ion species dependent) |
| Tilt angle | 0° – 60° | Suppresses channelling for standard implants; controlled channelling available for deep retrograde profiles |
| Pre-implant simulation | SRIM/TRIM dopant profile modelling included | Profile report before processing |
| RTA max temperature | 1800°C | Ar and N₂ atmospheres |
| Post-implant verification | Sheet resistance (4-probe), dose uniformity, particle count | Returned with wafer and process data report |
| Beam parallelism | ±0.5° or better | Critical for sub-micron device uniformity; parallel beam architecture |
| Carbon cap processing | Available | Required for SiC anneals >1400°C |
| SiC activation anneal | 1400–1800°C | Al and N activation for SiC MOSFET wells |
| GaN activation anneal | 700–1000°C | Mg p-type activation for GaN p-gate |
| Surface roughness | Low RMS achieved with carbon cap process | Critical for gate oxide quality on SiC |
Complete implant flow for 4H-SiC MOSFET fabrication, p-body, n+ source, p+ ohmic, plus 1800°C activation RTA with carbon cap. For EV inverters, industrial drives, and solar converters.
Implant isolation, Mg p-type gate, Si n-type ohmic contacts. E-mode (enhancement mode) GaN transistors for 5G RF and automotive power conversion.
P+ collector, N-drift, P-body, N+ emitter implants for IGBT fabrication. Base and emitter implants for bipolar transistors used in automotive and industrial power systems.
Piezoresistor implants for pressure sensors (boron in silicon), buried p+ stops for SOI MEMS, sacrificial layer doping, and polysilicon gate doping for capacitive sensors.
High-energy, high-concentration H implantation for Smart Cut™-type SOI substrate preparation. Hydrogen bubble layer formation at precise depth for layer separation and wafer bonding.
GaAs and InP device isolation by implantation, HBT base/emitter doping, InGaAs channel implants for photodetectors, and GaN-on-Si substrate engineering.
Most foundries offer standard room-temperature silicon implantation. What sets us apart is our ability to handle the complete power device implant flow, including the high-temperature steps and post-implant annealing that SiC and GaN devices demand.
600°C substrate heating during implantation, a capability most foundries lack. Without it, SiC MOSFET fabrication produces amorphous damage layers that cannot be activated regardless of anneal temperature.
The highest-temperature process step in SiC device fabrication is performed in our own facility. No need to ship wafers between vendors for the implant and activation anneal steps.
We stock over 60 dopant species including rare ones (Ca, Ba, La, Cl) not available at standard foundries. No lead time to source new dopant materials.
Every project includes a simulation run, not as an extra charge but as standard. This is how we guarantee your target doping profile is achievable before a single wafer is loaded.
Power device R&D and prototyping doesn't need 25-wafer lots. We process single wafers and small batches, making us accessible for academic research, startups, and low-volume production alike.
Ion implantation is followed directly by our etching, deposition, CMP, and bonding services. No cross-vendor handling, no contamination risk, no project coordination overhead.
Share your process requirements, substrate, and production volume, A Nanosystems JP Inc. engineer will respond within 1 business day. Full quote typically within 7–10 business days, subject to project complexity and NDA requirements.