PVD sputtering and e-beam evaporation are the deposition methods used in lift-off patterning flows. We offer the full lift-off service — resist, exposure, PVD deposition, and solvent strip — for Au, Pt, TiN, and AuSn multi-layer stacks.
Lift-off defines metal features by patterning resist first, depositing metal over the entire wafer, then dissolving the resist to leave metal only where the wafer surface was exposed. It avoids wet or dry etching of the metal entirely.
A positive photoresist is spin-coated on the wafer and exposed using the appropriate tool for the required feature size: contact aligner for features above 2µm, stepper for finer geometries. The exposure dose is tuned to produce a slight undercut in the developed profile, critical for clean metal separation during lift-off.
The exposed resist is developed to open windows where metal will be deposited. The sidewall profile - slightly re-entrant (undercut) - is verified by SEM cross-section for critical processes. The undercut prevents the deposited metal from bridging between the resist sidewall and the substrate, ensuring a clean break during lift-off.
Metal is deposited by PVD (sputtering or evaporation) over the entire patterned wafer. The deposition must be sufficiently directional so metal on the resist sidewalls is thin and discontinuous, allowing solvent to penetrate. Step coverage and deposition angle are controlled to optimize this. Au, Pt, Ti, TiN, AuSn, Ni, NiCr, and Al are all available.
The wafer is immersed in a solvent bath, commonly NMP (N-methyl-2-pyrrolidone) or acetone for standard photoresists, which dissolves the underlying resist layer and enables the overlying metal to lift off. This process removes unwanted material without the need for metal etching. Gentle agitation, including controlled ultrasonic assistance when appropriate, may be used to promote complete lift-off while preserving pattern integrity. The result is a patterned metal layer with well-defined features.
Lift-off is the right patterning method when the metal cannot be wet-etched - either because no selective etchant exists, because etch chemistry would damage underlying layers, or because the metal stack is too thin to mask reliably.
Au and Pt have no practical wet etchants compatible with photoresist. Aqua regia etches Au but attacks almost everything else. Lift-off is the standard patterning method for Au and Pt electrodes, bond pads, and contact metallisation.
AuSn 80/20 eutectic solder cannot be wet-etched without destroying the precise Au:Sn ratio required for 278°C eutectic behavior. Lift-off of a PVD Au/Sn multi-layer stack is the standard method for AuSn bump definition.
On devices where etch chemistry would attack a previously deposited layer - III-V compound semiconductor surfaces, piezoelectric films, or chemically sensitive bio-interfaces - lift-off avoids all wet metal etch steps entirely.
Neither lift-off nor etching is universally better. The right choice depends on the metal, the feature geometry, and the underlying layers. This table summarises the key decision factors.
| Factor | Lift-Off | Wet Etching | Dry (Plasma) Etching |
|---|---|---|---|
| Au, Pt, Ir, AuSn | ✓ Best option - no reliable etchant exists | ✗ No practical etchant | ✗ Very slow, re-deposition, chamber contamination |
| Al, Ni, Cr | ✓ Works well | ✓ Reliable, fast | ✓ Good option |
| Fine-pitch electrodes (<5µm) | ✓ Excellent - sharp sidewalls, no undercut | ✗ Isotropic etch causes undercut of features | ✓ Good, but mask required |
| Thick metal (>2µm) | ✗ Difficult - metal thickness must be < resist undercut | ✓ No thickness limit | ✓ No thickness limit |
| Sensitive underlying layers | ✓ No plasma damage, no chemical attack | ✗ Etchant may attack underlying material | ✗ Plasma can damage gate oxides, sensors |
| Multi-layer metal stacks | ✓ All layers deposited in one PVD run, lifted together | ✗ Each layer needs its own etch step | ✗ Each layer needs its own etch step |
| Edge sharpness | ✓ Defined by resist, not etch isotropy | ✗ Undercutting degrades edge definition | ✓ Good vertical sidewalls possible |
All metals are deposited by PVD (sputtering or evaporation) depending on the material and target film properties. Stacks (e.g. Ti/Au, Ti/Pt, TiW/Au) are available for adhesion layer + functional metal in a single lift-off step.
| Metal / Stack | Deposition Method | Typical Thickness | Primary Applications |
|---|---|---|---|
| Ti/Au | Sputter (Ti) + sputter or e-beam evap (Au) | 10–50nm Ti / 50–500nm Au | Bond pads, electrodes, RF contacts, ohmic contacts |
| Ti/Pt | Sputter (Ti) + sputter (Pt) | 10–30nm Ti / 50–200nm Pt | Biomedical electrodes, MEA, neural probes, MEMS sensors |
| AuSn 80/20 | PVD multi-layer (Au/Sn stacked layers) | 1–5µm total stack | Eutectic bump definition for flip-chip, hermetic sealing |
| Ti/TiN | Reactive sputter | 20–100nm Ti / 50–200nm TiN | Diffusion barriers, UBM adhesion layers |
| Ni / NiCr | Sputter or e-beam evaporation | 50–500nm | Thin-film resistors, UBM, solderable surfaces |
| Al / AlCu | Sputter | 100nm–2µm | Interconnect metal, MEMS structural layers |
| TiW/Au | Sputter | 50nm TiW / 100–300nm Au | UBM for AuSn and SnAg solder, RDL seed layers |
Other metals and custom stacks available on request. Minimum feature size and maximum film thickness are interdependent - contact us with your specific requirements.
Au and Pt microelectrode arrays (MEAs) for neural recording, retinal implants, and lab-on-chip biosensors are patterned by lift-off. The electrodes must be noble metal to resist corrosion in physiological fluids - wet etching is not viable for either material.
RF MEMS switches, SAW/BAW resonator contact pads, and ohmic contacts on GaAs and GaN devices use Au or Ti/Au lift-off metallisation. The underlying III-V or piezoelectric substrate would be attacked by Au etchants, making lift-off the only compatible patterning approach.
Wafer-level AuSn eutectic bumps for flip-chip bonding of laser diodes onto silicon photonic PICs, MEMS hermetic sealing, and RF MEMS packaging are defined by PVD lift-off. The exact Au:Sn ratio is set by the deposited layer thicknesses - something wet etch cannot preserve.
Under-bump metallisation (UBM) and redistribution layer (RDL) seed layers are often defined by lift-off of Ti/Au or TiW/Au stacks before electroplating. Lift-off provides the fine pitch capability and clean edge definition needed for sub-50µm pitch UBM on advanced packaging wafers.
🟣 Flexible & metallic substrates: Liftoff patterning is also available on polyimide (PI) film and thin SUS stainless steel substrates for flexible sensor and thin-film thermocouple fabrication.
Learn more →Share your process requirements, substrate, and production volume, A Nanosystems JP Inc. engineer will respond within 1 business day. Full quote typically within 7–10 business days, subject to project complexity and NDA requirements.