At Nanosystems JP Inc., we offer complete packaging and assembly services, including backgrinding, dicing, die bonding, wire bonding (Au/Al/Cu from 18 µm to 500 µm), flip-chip (five bump systems), BEOL Cu CMP, and full 3D/2.5D IC integration with TSV, TGV, RDL, UBM, and C4 bumping.
Most packaging houses specialize in one or two assembly steps, requiring customers to coordinate multiple vendors. We provide the complete flow, from backgrinding the finished wafer through every assembly step to bumped, bonded, or wire-bonded final device.
Every step from backgrinding to final packaged device is managed as one project. no inter-vendor wafer transfers, no re-quoting between steps, no schedule mismatches when one step finishes early or late. Your wafer progresses through the full assembly sequence as a single managed project.
Backgrind thickness, dicing kerf quality, die attach bond strength, wire bond pull/shear, flip-chip alignment, and UBM coverage, each step has a defined inspection gate before the wafer advances. Process data is recorded and provided in the final lot report. Non-conforming material is quarantined and reported before the next step begins.
We handle the complete transition from wafer-level processing to module-level device, the most logistically complex phase of semiconductor manufacturing. Thin wafers, small dies, fragile MEMS structures, photonic chips requiring micron-level placement, all handled with the process discipline that precision devices require.
Before any die-level assembly, the wafer must be thinned and singulated. Both steps are performed and coordinated as part of the same project, no separate dicing house required.
Backside grinding reduces wafer thickness from the standard 700µm down to the target for packaging. For standard packages, 100–200µm is typical. For TSV reveal and 3D-IC stacking, grinding to 50µm is required, with carrier wafer support to prevent fracture of the thinned substrate. Coarse grinding removes bulk silicon; a subsequent fine-polish or stress-relief CMP step removes the sub-surface damage layer that would become a fracture initiation site in thinned wafer handling. Target thickness controlled to ±2µm within-wafer uniformity. Wafer thickness map is provided post-grind.
Four dicing methods available for different material and die geometry requirements. Standard blade dicing for rectangular Si/glass dies on 4–12 inch wafers. Stealth laser dicing (dry, no water, no dicing debris) for silicon photonics PICs and fragile MEMS where blade dicing water and swarf cause contamination and membrane damage. Diamond scribing for brittle compound semiconductors (SiC, AlN, InP) that chip under blade contact. Large-format glass dicing to 500×600mm for glass interposers and biochip substrates. Post-dicing inspection, die sorting by wafer map, and JEDEC tray packing all included.
Die bonding mechanically and thermally connects the singulated die to its package substrate, carrier, or PCB. The attach material determines thermal resistance, temperature rating, reworkability, and process temperature.
Thermally or UV-curable epoxy paste dispensed by automated dispenser and cured at 120–200°C. The standard approach for cost-sensitive applications, compatible with any die size from sub-mm up to large power dice. Conductive epoxy (silver-filled) provides simultaneous mechanical and electrical connection; non-conductive epoxy for electrically isolated die attach. Void percentage in the bond line verified by C-SAM acoustic inspection for power devices where void-induced hot spots cause premature failure.
AuSn eutectic die attach at 278°C provides a hermetic, void-free bond with far higher thermal conductivity than epoxy (57 W/m·K vs ~3 W/m·K for silver epoxy). Essential for laser diodes (InP, GaAs) where heat extraction directly from the active layer determines lifetime, and for optical MEMS requiring hermetic die attach without organic outgassing near optical surfaces. AuSn also serves as a reliable attach for SiC power devices operating at junction temperatures above 200°C.
Sintered silver paste pressed and sintered at 200–280°C under applied pressure, forming a porous silver matrix with thermal conductivity over 200 W/m·K and operational temperature to 300°C+. The emerging standard for SiC and GaN power modules replacing solder die attach in next-generation electric vehicle inverters and industrial drives. Bond strength exceeds most solder systems. No reflow temperature constraint, critical for SiC devices with 175°C+ rated junction temperatures.
Wire bonding connects die pads to package leads or substrate pads using a thin metal wire compressed and thermally bonded at each end. Three metal systems are available, matched to temperature, current, and reliability requirements.
Flip-chip inverts the die and bonds it face-down directly to the substrate via pre-formed bumps, eliminating bond wire parasitics and reducing package footprint. Five bump metallurgies are available.
Bumps are formed by electroplating (Cu, SnAg, NiSn) through a photoresist mask before flip-chip bonding, or by electroless plating (NiAu / ENIG, NiPd / ENEPIG) for UBM surface preparation. AuSn bumps are deposited by PVD with lift-off patterning as described in our dedicated AuSn bump service. Stencil printing of solder paste is available for larger bump pitches (>200µm).
Die placed face-down on substrate using automated flip-chip bonder with optical alignment to substrate fiducials, placement accuracy ±2µm for standard bump pitches. Thermocompression bonding for AuSn and Cu pillar; reflow oven for SnAg C4. Self-aligning reflow uses solder surface tension to correct pick-and-place offset, achieving final alignment better than the initial placement accuracy for eutectic solder systems.
After flip-chip bonding, joint quality is verified by X-ray inspection (solder void percentage, bridging between adjacent bumps) and acoustic microscopy (delamination at the die-substrate interface). For optical flip-chip (AuSn laser bonding), coupling efficiency measurement is used as the functional acceptance criterion. Daisy-chain test structures on engineering wafers verify electrical continuity of the entire bump array before production bonding.
Beyond wire bond and flip-chip, we provide the full advanced packaging stack for 3D-IC and 2.5D chiplet integration , all coordinated in the same coordinated project.
CVD dielectric deposition over completed device wafer followed by lithography and dry etch to define via holes and metal trenches. For single damascene, via and trench etched separately. For double damascene, combined in one dual-pattern etch step. Low-k CVD dielectric (SiOCH) available to reduce RC delay in fine-pitch BEOL interconnects above 10 GHz.
Barrier/seed sputtering into trenches followed by superfill Cu electroplating. Bottom-up fill prevents seam voids that create high-resistance line segments. Post-plate anneal at ~400°C for grain stabilisation and stress relief before CMP removes overburden. Same process as TSV fill, the same team handles both wafer-scale Cu electroplating steps.
Cu CMP removes overburden and stops on the dielectric using eddy current endpoint. Cu dishing within wide lines and dielectric erosion between closely spaced lines are measured and reported. The planarised surface is the starting point for the next dielectric layer or for RDL/UBM deposition in a packaging flow.
| Service | Specification | Notes |
|---|---|---|
| Wafer Backgrinding | Target thickness 50–700µm | ±2µm uniformity; carrier wafer for <150µm |
| Dicing, Blade | Si/glass 4–12 inch; glass panels to 500×600mm | Standard rectangular dies |
| Dicing, Stealth Laser | Si wafers; polygon dies (hex, octagon) | Dry process, no water, no debris |
| Dicing, Diamond Scribing | SiC, AlN, InP, GaAs | Brittle compound semiconductors |
| Die Bonding, Epoxy | Conductive Ag-filled or non-conductive | 120–200°C cure; C-SAM void inspection |
| Die Bonding, AuSn Eutectic | 278°C, hermetic, void-free | Laser diode, SiC, optical MEMS |
| Die Bonding, Ag Sinter | >200 W/m·K, 200–280°C sinter | SiC/GaN power modules |
| Wire Bonding, Au | 18–75µm; ball bonding; <50µm pad pitch | RF, analog, sensors; fine-pitch capable |
| Wire Bonding, Al (fine) | 25–75µm; wedge bonding; no heat | Temperature-sensitive devices; MEMS |
| Wire Bonding, Al (heavy) | 125–500µm; wedge bonding | SiC, IGBT, GaN power, high current |
| Wire Bonding, Cu | 18–75µm; ball bonding; forming gas N₂/H₂ | Automotive, consumer IC; PCC wire option |
| Flip-Chip, AuSn | 278°C fluxless; ±1µm alignment (SiPho) | Laser diode, MMIC, MEMS hermetic |
| Flip-Chip, SnAg (C4) | 217–221°C; self-aligning reflow | Standard CSP/BGA flip-chip to organic |
| Flip-Chip, NiSn/NiAu/NiPd | Electroless plating; wire-bond compatible | WLCSP, CSP, ENIG/ENEPIG surface |
| BEOL Cu Damascene | Single and double damascene | CVD SiO₂ or low-k; superfill Cu CMP |
| TSV / TGV | TSV: DRIE 50:1; TGV: to 510×510mm | Full 5-step flow; reveal available |
| RDL Fabrication | BCB/PBO/PI polymer or Cu damascene | Fan-in WLCSP or fan-out FOWLP |
| UBM | ENIG or ENEPIG | Solder wetting + diffusion barrier |
| C4 Bumping | SnAg by electroplating; self-aligning | Pitch from 150µm; flip-chip to substrate |
AuSn flip-chip of GaAs/InP/GaN MMIC chips onto high-frequency ceramic or laminate substrates. Au ball wire bonding for RF input/output lines. Hermetic package sealing by eutectic or glass frit bonding. Used in 5G/6G front-end modules, phased array radar, and satellite communication terminals.
AuSn flip-chip of InP/GaAs laser dies onto SiPho PIC (±1µm self-aligning), Cu wire bonding of EIC (electronic IC) to PIC, AuSn die attach of PIC to AlN carrier for thermal management, and C4 bumping of the full module to package substrate. Complete photonic co-packaging flow .
Ag sinter die attach of SiC MOSFET and GaN transistor chips for maximum thermal conductivity. Heavy Al wire bonding (500µm) for high-current source connections. Au wire bonding for gate signals. DBC (direct bonded copper) substrate assembly. Gel-fill or transfer mold encapsulation. For automotive traction inverters and industrial motor drives.
TSV + RDL + C4 bumping for full 3D-IC and 2.5D chiplet stacks, HBM memory on logic, MEMS-on-CMOS, and multi-die silicon interposer assembly. All steps from TSV reveal through chiplet flip-chip to final C4 bumping for substrate attach managed as one project.
WLCSP fan-in RDL for MEMS inertial sensors (accelerometers, gyroscopes, pressure sensors), eliminating bond wires and enabling direct PCB mount. Hermetic MEMS cap bonding by anodic or glass frit bonding before dicing. Wire bonding for non-WLCSP MEMS packages. Stealth laser dicing to protect fragile MEMS membranes.
Backside-illuminated (BSI) image sensor assembly, TSV reveal for backside contacts, RDL, and C4 bumping for flip-chip to carrier substrate. Wire bonding of digital interface. Stealth laser dicing to singulate thin BSI wafers without water contamination of the optical surface. Used in smartphone, automotive, and scientific cameras.
Biocompatible Au wire bonding and AuSn hermetic package assembly for implantable neural interfaces, retinal implants, cochlear implants, and deep brain stimulators. Polyimide RDL for flexible probe variants. Hermetic ceramic-to-metal package sealing. NDA-protected, IP remains with the customer.
AuSn flip-chip of micro-LED and laser projector arrays onto waveguide display substrates for AR/VR headsets. Cu pillar flip-chip for high-density driver IC bonding to display backplane. Stealth laser dicing of optical die to preserve facet quality. Wire bonding of control ICs in compact optics modules.
Au wire bonding with MIL-STD-883 and ESCC-compliant process controls for space-grade electronics. Hermetic ceramic package assembly. 100% destructive pull testing on witness samples. Radiation-tolerant die handling procedures. Lot traceability from raw die to completed package. Export-controlled handling where required.
Backgrinding, dicing, die bond, wire bond, flip-chip, BEOL, TSV/TGV, RDL, UBM, and C4 bumping, . no inter-vendor wafer transfers between any assembly step. The most common source of yield loss in advanced packaging is contamination, surface oxidation, and mechanical damage during inter-vendor shipping of thin, delicate wafers.
Fine Au wire (18µm) for RF and sensor fine-pitch bonding through to heavy Al wire (500µm) for SiC and GaN power device high-current connections, a 28× range of wire diameter covering every application from microwave ICs to traction inverters. Both capabilities in the same coordinated project, coordinated in the same project when a device uses both.
Specialist AuSn flip-chip bonding with ±1µm self-aligning accuracy for silicon photonic PIC assembly, including cavity wafer support for pre-etched laser placement pockets. This is not a standard capability at assembly houses; it requires PVD bump fabrication and thermocompression bonding expertise that general packaging foundries do not have.
500µm Al heavy wire bonding for SiC MOSFET and GaN power modules, the same coordinated project handling both the SiC wafer-level processing (ion implantation, annealing) and the final power module assembly. The engineering team understands SiC device requirements at both ends of the manufacturing flow.
The largest glass interposer TGV capability available: 510×510mm panel format. Customers building panel-format glass interposers for RF or optical applications do not need a separate TGV vendor. RDL and C4 bumping follow TGV in the same coordinated project.
Packaging designs, die layout, wire bond map, bump pitch, flip-chip alignment targets, are highly proprietary. An NDA can be arranged before any design files are shared - just mention it in your first message. Initial inquiries and quotes can proceed without one. Pure-play foundry: we do not design, manufacture, or sell packaged devices that compete with our customers' products.
Share your process requirements, substrate, and production volume, A Nanosystems JP Inc. engineer will respond within 1 business day. Full quote typically within 7–10 business days, subject to project complexity and NDA requirements.