Specialty Bump Services, Silicon Photonics & Advanced Packaging

AuSn Bump Services
for Silicon Photonics (PIC)

At Nanosystems JP Inc., we offer wafer-level Gold-Tin (AuSn) bumping via two complementary routes, PVD multi-layer thin film (stacked, co-deposition, or direct alloy target) with lift-off patterning, and AuSn electroplating with tunable composition. Eutectic 80/20 and custom alloys. 4–12 inch wafers and cavity wafers. Fluxless hermetic bonding for photonic flip-chip assembly.

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PVD stacked Au/Sn Co-deposition PVD Direct alloy target Lift-off patterning AuSn electroplating Eutectic 80/20 (Au:Sn wt%) Custom 75/25 · 70/30 Cavity wafer support

Anatomy of a Perfect Bond

Anatomy of a Perfect Bond - AuSn eutectic bump stack cross-section showing Eutectic AuSn Bump, ENIG/ENEPIG pad finish, UBM Ti/Ni/Au multi-layer stack, RDL, and Silicon/PIC substrate

Deposition routes:
PVD & electroplating

4–12″

Wafer sizes supported
incl. cavity wafers

80/20

Standard eutectic
Au:Sn composition (wt%)

Fluxless

Hermetic bonding -
no flux residue

Why AuSn for Silicon Photonics

Wafer-level AuSn bump fabrication
for photonic flip-chip assembly

We fabricate AuSn bumps on your wafer - PVD multi-layer with lift-off, or electroplating - delivering a bumped wafer ready for flip-chip assembly at your facility or your assembly partner. AuSn is the industry-standard solder for photonic device integration because of three properties that conventional SnAg cannot provide.

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Fluxless - No Optical Contamination

Standard flip-chip solders require flux to remove native oxide before bonding, but flux residue near optical waveguide facets scatters light and degrades coupling efficiency. AuSn is inherently fluxless: the gold surface does not form a refractory oxide, so the native Sn oxide is consumed by the gold during reflow without any chemical flux. The optical facet stays clean after bonding.

No flux required No optical contamination Waveguide facet protected Coupling efficiency maintained

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Hermetic - Moisture Barrier

AuSn forms intermetallic compounds (Au₅Sn and AuSn) during reflow that are rigid, high-melting, and impermeable to moisture. This provides a true hermetic seal - a requirement for telecom-grade laser reliability (Telcordia GR-468), where even ppm-level moisture causes mirror degradation in InP laser diodes over a 25-year operational lifetime.

True hermetic seal Au₅Sn + AuSn IMC Moisture barrier Telcordia GR-468 compatible 25-year laser reliability

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Self-Aligning - ±1µm Placement

During reflow above 278°C, molten AuSn surface tension pulls the die into alignment with the waveguide, correcting pick-and-place errors. For a Si waveguide mode field diameter of 2–3µm, even ±0.5µm lateral misalignment reduces coupling by >3dB. Bumps fabricated to the correct geometry and composition enable ±1µm self-alignment during your assembly reflow.

Self-aligning on reflow ±1µm capable Surface tension driven Corrects pick-place error 2–3µm mode field compatible

Two Fabrication Routes

PVD thin film and electroplating -
matched to your application

Both routes deposit the same eutectic AuSn alloy but use different physics, enabling different trade-offs in composition control, bump height, throughput, and feature resolution. Our engineers recommend the optimal route based on your PIC platform and bump geometry.

AuSn eutectic bump wafer - UBM Ti/Pt/Au layers with gold-tin bumps

PVD Multi-Layer Thin Film Deposition

STACKED · CO-DEPOSITION · DIRECT ALLOY · LIFT-OFF

Physical Vapor Deposition (PVD) deposits gold and tin sequentially or simultaneously from sputtering or evaporation targets. The alloy composition is precisely controlled by the relative thickness or deposition rate of each layer. After deposition, lift-off lithography defines the bump pattern with submicron dimensional accuracy, no wet metal etching required. This is the premier route for applications requiring the highest compositional precision and finest feature definition. Alloy compositions including eutectic 80/20, 75/25, 70/30 wt%, and other custom off-eutectic ratios are achievable by adjusting individual layer thicknesses.

Three PVD sub-routes are available, each with different trade-offs in process complexity, composition uniformity, and throughput:

Stacked Au/Sn Layers

Alternating Au and Sn layers deposited sequentially to achieve target stoichiometry. Subsequent reflow above 278°C causes interdiffusion forming uniform Au-Sn intermetallic compounds. Most robust for thick bump stacks. Composition set by layer thickness ratio.

Co-Deposition

Au and Sn simultaneously co-sputtered from two independently controlled targets. Real-time composition control by target power, enables direct alloy formation without separate reflow interdiffusion. Excellent uniformity across the wafer. Preferred for precise off-eutectic compositions.

Direct Alloy Target

Pre-alloyed AuSn target (80/20 or custom ratio) sputtered directly. Simplest process, single target, fixed composition per deposition run. Highest film purity. Best for standard eutectic bumps where composition flexibility is not needed.

Highest composition precision Lift-off, no wet etch Sub-µm dimensional accuracy Fine pitch capable Void-free interface Best for SiPho laser bonding

AuSn Electroplating

CO-DEPOSITED · TUNABLE COMPOSITION · THICKER BUMPS

AuSn electroplating deposits gold and tin simultaneously from a proprietary co-plating electrolyte, achieving the target alloy composition in a single plating step. The composition is controlled by the electrolyte chemistry and current density. Electroplating enables significantly thicker bump heights than PVD (5–50µm vs 0.5–5µm for PVD), which is important for applications requiring large solder volume for thermal compliance or reworkability.

Electroplating through a photoresist mask defines the bump pattern, the resist is stripped after plating and the seed layer is etched, leaving freestanding AuSn bumps. Compositional tuning between different runs is achieved by adjusting electrolyte ratios, enabling 80/20, 75/25, 70/30 or custom off-eutectic alloys without changing target materials as in PVD.

Parameter	PVD Thin Film Deposition	Electroplating
Bump height	0.5–5µm typical	2–50µm typical
Composition control	±0.5 wt% (excellent)	±1–2 wt% (good)
Feature size	Sub-µm (lift-off)	~5µm min (plating)
Throughput	Lower (sequential dep.)	Higher (batch plating)
Best for	Fine pitch, precision SiPho	Larger bumps, RF/MMIC, volume

Thicker bumps: 5–50µm Tunable composition Higher throughput Cost-effective for volume Best for RF/MMIC, MEMS

AuSn Alloy Compositions

Standard eutectic and custom
off-eutectic alloys available

The Au:Sn ratio determines the melting point, microstructure, mechanical properties, and thermal fatigue resistance of the solder joint. We offer the standard eutectic and three off-eutectic compositions, custom ratios available on request.

Alloy composition options

80/20 eutectic is standard, off-eutectic for specific thermal and mechanical needs

The eutectic 80Au:20Sn composition melts at 278°C with minimal melting range, simplifying reflow process control. Off-eutectic compositions shift the melting point and change the ratio of Au₅Sn to AuSn intermetallic phases, which affects joint ductility, thermal fatigue life, and compatibility with subsequent high-temperature processes.

80/20

Au:Sn wt% · EUTECTIC

Melting point: 278°C

Standard for SiPho laser bonding, VCSEL, and hermetic RF packages. Narrowest melting range, best reflow control.

75/25

Au:Sn wt% · Sn-RICH

Liquidus: ~340°C

Higher Sn content increases joint ductility. Used where thermal fatigue resistance is prioritised over low bonding temperature.

70/30

Au:Sn wt% · Sn-RICH

Liquidus: ~380°C

For applications requiring high-temperature second-level reflow compatibility after AuSn bonding. More ductile than eutectic.

Custom

Any Au:Sn ratio

Engineered melting point

Custom composition for specific thermal hierarchy requirements, reflow temperature constraints, or mechanical property targets. On request.

Eutectic 80/20 available by PVD and electroplating, both routes

Off-eutectic 75/25 and 70/30 available by electroplating and co-deposition PVD

Custom composition on request, specify Au:Sn ratio or target melting point

Composition verified by XRF (X-ray fluorescence) measurement after deposition

Microstructure verification by cross-section SEM + EDX after reflow

Au₅Sn and AuSn IMC phase ratio reported in process data sheet

Reflow profile optimisation for your bonding equipment and thermal budget

Cavity wafer support, bump height adapted for recessed laser placement

Lift-Off Patterning

Why lift-off, not wet etch defines AuSn bump geometry

AuSn is notoriously difficult to wet etch without undercutting the Au and compromising bump geometry. Lift-off avoids the problem entirely, and achieves better dimensional accuracy.

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The Lift-Off Process

A photoresist layer is patterned by lithography before any metal deposition. AuSn is then deposited (PVD) over the entire wafer, covering both the open bump areas and the resist. The resist is dissolved in solvent (lift-off), carrying away the metal deposited on top of it and leaving AuSn only in the photolithographically defined bump areas. No acid etch contacts the final AuSn bump surface, preserving purity and dimensional accuracy.

Resist patterned first PVD over resist Solvent lift-off No acid etch on AuSn Clean bump surface Sub-µm edge definition

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Dimensional Accuracy

Lift-off defines bump geometry by the photoresist opening, the same lithography that defines the waveguide layer of the PIC. Bump width, spacing, and alignment to underlying bond pads are controlled by lithographic registration accuracy (±0.5µm on our stepper). Wet etch of AuSn always produces lateral undercut that enlarges the gap between bumps and makes fine-pitch arrays impossible. Lift-off has no undercut.

±0.5µm registration stepper alignment No undercut Fine-pitch arrays possible Bump width = resist opening

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Post-Lift-Off Inspection

After lift-off and before reflow, bump height uniformity is measured across the wafer by profilometry, height variation less than ±5% is required for uniform reflow across a wafer with thousands of bump sites. Bump geometry is verified by SEM. After reflow, the AuSn bump intermetallic microstructure is characterized by cross-section SEM and EDX to confirm phase composition and void-free interface quality.

Profilometry height map ±5% uniformity spec SEM geometry check Post-reflow SEM + EDX Void-free interface confirmed

Cavity Wafer Support

Laser diode placement in
Si-etched pockets

Many silicon photonic platforms place the laser diode inside a pre-etched silicon cavity, reducing the height offset between the laser waveguide and the silicon waveguide. Our AuSn bumping is adapted for cavity wafer geometry.

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Why Cavities Are Used

A standard silicon photonic waveguide sits approximately 3–5µm below the top surface of the Si wafer. An InP laser diode's active layer is typically 2–3µm above the bottom of the chip. To align the two waveguides vertically, the laser must either sit on a very thin bump (difficult to control) or sit inside a pre-etched Si cavity that positions its waveguide at exactly the right height. Cavity depth is typically 5–20µm and is defined by DRIE or wet KOH etching before wafer-level bumping.

Cavity depth 5–20µm DRIE or KOH pre-etch Waveguide height alignment Vertical coupling optimized Bump height adapted to cavity

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Adapted Bumping Process

Cavity wafers require modified lithography and PVD deposition conditions compared to flat wafers. The resist coating must be thick enough to planarize over the cavity walls. PVD step coverage into the cavity must be controlled to achieve uniform AuSn thickness on the cavity floor bond pads. Post-lift-off inspection includes profilometry across both the cavity and flat regions to confirm uniform bump height. Cavity wafer bumping is a standard service, not a special request requiring process development.

Thick resist over cavity PVD step coverage adapted Cavity + flat profilometry Standard service offering InP/GaAs laser die placement

Process Specifications

Complete AuSn bump
fabrication parameters

Parameter	PVD (Stacked/Co-dep/Direct)	Electroplating
Wafer Sizes	4 inch (100mm), 6 inch (150mm), 8 inch (200mm), 12 inch (300mm)
Cavity Wafer Support	Yes, both routes
Primary Materials	Gold (Au), Tin (Sn)
Standard Composition	Eutectic AuSn 80/20 wt%
Custom Compositions	75/25, 70/30, and other ratios on request
Bump Height	0.5–5µm typical	2–50µm typical
Minimum Bump Size	~5µm (lift-off limited)	~20µm (resist limited)
Height Uniformity	±5% within-wafer	±8% within-wafer
Patterning Method	Lift-off (all 3 sub-routes)	Through-resist plating + seed etch
Lithography	stepper and mask aligner	stepper and mask aligner
Alignment Accuracy	±0.5µm (stepper)	±1µm
Reflow Temperature	Above 278°C (80/20 eutectic)
Bonding Type	Fluxless, hermetic
Post-Deposition Inspection	Profilometry + SEM	Profilometry + SEM
Post-Reflow Inspection	Cross-section SEM + EDX (IMC phase verification)
Thermal Conductivity (AuSn)	~57 W/m·K (5× higher than SnAg)
Melting Point (80/20)	278°C (eutectic, narrow melting range)

Applications

AuSn bump across photonics,
RF, and precision electronics

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Silicon Photonics PIC Assembly

AuSn flip-chip bonding of InP or GaAs laser sources to Si photonic integrated circuits, placing the laser waveguide facet within ±1µm of the Si waveguide input via self-aligning reflow. The primary application driving AuSn bump technology. Used in 400G/800G/1.6T optical transceiver co-packaged optics modules.

InP/GaAs → Si PIC · ±1µm · Self-align · 400G–1.6T transceivers

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Laser Diode Packaging (DFB / VCSEL)

Telecom DFB and VCSEL laser die flip-chip bonded to AlN or Si carrier substrates using AuSn eutectic. AuSn's high thermal conductivity (57 W/m·K vs 33 W/m·K for SnAg) reduces thermal resistance from the active region to the heat sink, critical for single-mode laser reliability and wavelength stability.

DFB · VCSEL · AlN carrier · Thermal conductivity · Wavelength stability

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RF / MMIC Flip-Chip

Fluxless AuSn bumping for GaAs, InP, and GaN MMIC flip-chip assembly onto high-frequency substrates. Flux-free is mandatory at millimetre-wave frequencies: even trace flux residue changes the dielectric environment of the transmission lines and degrades return loss. Used in 5G/6G front-end modules, phased array T/R modules, and mmWave radar chips.

GaAs · InP · GaN MMIC · Fluxless · 5G/6G FEM · mmWave radar

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MEMS Hermetic Packaging

AuSn eutectic at 278°C seals MEMS resonators, gyroscopes, optical MEMS mirrors, and MEMS pressure sensors hermetically, below 300°C to preserve CMOS compatibility and avoid piezoelectric material degradation. AuSn's hermetic seal meets automotive and aerospace leakage specifications for MEMS inertial sensors.

MEMS resonator · LIDAR mirror · Gyroscope · <300°C · Hermetic

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Power Semiconductor Die Attach

AuSn die attach for SiC MOSFET and GaN transistor chips in hermetic packages. The AuSn intermetallic compound remains solid and mechanically stable above 600°C, far beyond SnAg's operational limit (~250°C). Essential for high-junction-temperature SiC devices in traction inverters and industrial drives.

SiC MOSFET · GaN · Hermetic · High-temp stable >600°C · Traction

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IR Detector Array Bonding

AuSn flip-chip bonding of InGaAs, HgCdTe, and quantum dot photodetector arrays to silicon ROIC (readout integrated circuit) for IR cameras, hyperspectral imaging sensors, and LiDAR receivers. Fine-pitch AuSn bump arrays (50–150µm pitch) by PVD lift-off enable pixel pitches required for high-resolution focal plane arrays.

InGaAs · HgCdTe · QD detector · ROIC · IR camera · LiDAR receiver

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AR/VR Photonic Integration

AuSn bonding of micro-LED arrays and laser projector dies onto waveguide display substrates for augmented and virtual reality headsets. AuSn self-alignment during reflow positions the emitter facets accurately over the waveguide coupler, critical for the compact collimation optics in near-eye displays.

µ-LED · Laser projector · Waveguide display · AR/VR · Near-eye

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Optical MEMS (LIDAR Mirrors)

Hermetic AuSn packaging of MEMS scanning mirrors for automotive and industrial LIDAR, sealing the mirror in vacuum or inert atmosphere to maintain resonance quality factor. AuSn at <300°C preserves the silicon MEMS structure after CMOS backend completion.

MEMS mirror · LIDAR · Vacuum seal · AuSn <300°C · Automotive

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Biomedical Implantable Optics

AuSn hermetic sealing of optical transceivers in implantable neural interfaces, retinal implants, cochlear implants, and deep brain stimulators. AuSn biocompatibility (gold and tin are both biocompatible), hermeticity, and low bonding temperature make it the preferred solder for implant-grade hermetic optical packages.

Neural implant · Retinal · Cochlear · Hermetic · Biocompatible · DBS

Why Nanosystems JP Inc.

What makes our AuSn bump capability
different

Three PVD routes, one coordinated process flow

Stacked Au/Sn layers, co-deposition, and direct alloy target, all three PVD sub-routes available . Our engineers select the optimal route for your composition tolerance, bump height, and throughput requirements, not constrained to a single PVD method.

Lift-off for sub-micron bump definition

Lift-off patterning achieves bump width and pitch accuracy that wet etching of AuSn cannot match. stepper lithography provides ±0.5µm alignment accuracy, matching the precision required for silicon photonic waveguide coupling where bump position determines optical coupling efficiency.

Cavity wafer bumping as standard

Silicon photonic platforms with pre-etched laser placement cavities require adapted resist coating, PVD deposition, and inspection, we run cavity wafer bumping routinely as a standard service. Not a special request requiring weeks of process development.

Custom compositions available

Beyond 80/20 eutectic: 75/25, 70/30, and fully custom Au:Sn ratios for specific melting points, IMC phase ratios, and mechanical property targets.

SiPho platform context understood

We understand the silicon photonics assembly context, waveguide mode field diameter, laser facet cleave angle, vertical coupling tolerance, and reflow self-alignment mechanics. AuSn bumping is designed as a component of the full PIC assembly flow, not as an isolated plating service.

From 1 wafer, no minimum lot

Prototype AuSn bumping on a single wafer, verify composition, bump height uniformity, and reflow microstructure before committing to volume. Same process recipe scales to production with the prototype data as the baseline. No re-qualification required.

AuSn Bump Servicesfor Silicon Photonics (PIC)