Deep Silicon Etching
and Through-Wafer DRIE
Trenches, cavities, blind vias, and through-wafer structures by the Bosch process: aspect ratios above 50:1 on narrow features, depths of 100 µm and more, sidewalls at 89-90°, on 2-12-inch wafers. Send a cross-section and receive an initial engineering response typically within one business day.
narrow features
through-wafer
angle
diameters
What we etch
Deep silicon etching is one process family with several distinct products. Each has its own drawing requirements and inspection.
Trenches and combs
Straight or curved trenches for MEMS springs, comb drives, and isolation; widths from a few micrometers, depths to the full device layer or hundreds of micrometers.
Cavities and membranes
Backside cavities for pressure-sensor and microphone membranes, etched to a buried oxide or a timed depth; frontside pockets for optical or fluidic elements.
Blind vias and TSVs
High-aspect-ratio holes for through-silicon vias, later lined, seeded, and filled with copper; see the TSV page for the complete flow, and the thick-substrate section below for through-vias in silicon up to about 1.5 mm.
Through-wafer holes and release
Holes and slots through the full wafer thickness for fluidics, optical access, and die release; handled on carriers where the wafer is thinned.
SOI device layers
Etch to the buried oxide with notching control at the interface; device-layer thicknesses from a few micrometers to hundreds.
Glass and other materials
For glass vias see TGV fabrication; for compound semiconductors and nitrides see ICP-RIE etching.
Deep Silicon Etching and Through-Wafer DRIE
Scope and specification options. Every figure is confirmed for your program in the quotation.
Typical width and depth combinations
Achievable depth and profile depend on width, pattern density, and the stop layer. The table gives combinations we routinely quote; everything else is confirmed at engineering review.
| Feature width | Typical depth | Aspect ratio | Notes |
|---|---|---|---|
| 3 to 5 µm | 100 to 200 µm | Above 50:1 for selected geometries | TSV and fine trenches; liner route depends on aspect ratio, profile, film material, and coverage requirements |
| 10 µm | 350 µm | 35:1 | Design example (illustrative geometry) requiring near-vertical sidewalls: a 1° inward taper would close a 10 µm opening at about 286 µm, so profile and depth are reviewed together; sidewall angle and scallop values are typical targets confirmed per lot |
| 25 µm and 50 µm (examples) | Full wafer, 400 µm and 725 µm | Depends on wafer thickness and opening width; confirmed for the proposed geometry | Through-wafer vias and fluidic holes; carrier or frame for thin wafers |
| 50 to 500 µm | Full wafer | Depends on wafer thickness and opening width; confirmed for the proposed geometry | Cavities, membranes, die release; loading effects managed by pattern layout |
| Device layer on SOI | 2 to 200 µm to buried oxide | per design | Notching control at the oxide interface |
| Parameter | Specification | Notes |
|---|---|---|
| Process | Bosch (SF₆ / C₄F₈ cycling) | Alternating etch and passivation steps |
| Sidewall angle | 89-90° | Near vertical; taper adjustable on request |
| Scallop amplitude | Below 100 nm | Smoothing cycles available for liner-critical vias |
| Mask | Photoresist or SiO₂ hard mask | Si:SiO₂ selectivity above 100:1 |
| Wafer size | 2 to 12 inch (300 mm) | Pieces and coupons for feasibility |
| Etch stop | Timed, buried oxide (SOI), or backside stop layer | Endpoint by time or optical emission per program |
| Uniformity | Depth measurement locations, sampling, and reporting agreed for each project | Loading and ARDE effects reviewed on your layout |
Thick-substrate through-silicon vias, to about 1.5 mm
Conventional TSV depths run from tens to a few hundred micrometers. Through-wafer vias in silicon up to about 1.5 mm thick are 5 to 20 times deeper, which places them in a specialized deep-etch regime: high-aspect-ratio etching over hours, mask integrity over the full etch time, deep via filling, and double-sided planarization of a mechanically sensitive substrate. Nanosystems JP Inc. offers this as a process development engagement, managed end to end by a dedicated project manager from etch through fill and planarization, with metrology at each stage.
- 01Prepare maskSubstrate preparation and mask patterning (thick photoresist or hard mask).
- 02Etch both sidesDeep Bosch DRIE, etched from both sides to meet at the wafer midplane; the second side is registered to the first-side features.
- 03Clean and insulateMask removal, cleaning, and sidewall preparation, including electrical insulation where the design requires it.
- 04Barrier and seedBarrier and conductive seed preparation.
- 05Plate CuCopper electroplating fill.
- 06PlanarizeDouble-sided planarization (grinding, polishing, CMP as required).
- 07InspectMetrology and inspection.
| Parameter | Capability |
|---|---|
| Substrate | Silicon, thickness up to about 1.5 mm; other substrates on inquiry |
| Via format | Round vias and elongated slot vias |
| Through-thickness aspect ratio | 10:1 through the full thickness (each side is etched to about half the thickness) |
| Etch process | Bosch DRIE, double-sided etch forming continuous through-wafer vias; second-side pattern registered to the first-side features |
| Via fill | Copper electroplating, after barrier and seed preparation; fill assessed by X-ray CT at the resolution and sampling agreed for the program |
| Planarization | Double-sided grinding and polishing; CMP on inquiry for tight planarity requirements |
| Metrology | Surface geometry by agreed optical or confocal methods; internal via geometry and fill assessed by methods suited to the structure, with X-ray CT resolution, inspection region, sampling, and acceptance criteria defined per program |
| Engagement | Process development program; parameters characterized and confirmed for each program |
Every step scales with depth. Etch times run to hours per side, which stresses mask materials; 10:1 through-thickness aspect ratios drive etch-rate and via-width non-uniformity; a thick wafer populated with through-vias becomes mechanically fragile; and deep vias need specialized filling to reach copper fill without defects above the agreed detection limit. These effects have been characterized and process controls are refined at each stage.
Thick interposers and carriers
Interposers and carrier substrates for advanced packaging where stiffness or thickness is part of the design.
Feedthroughs
Through-wafer electrical feedthroughs for MEMS and sensor substrates, hermetic feedthroughs, and vacuum packaging.
RF, power, and photonics substrates
Thick substrates with vertical connections for RF, power, and photonic modules.
AI/HPC and automotive packaging
Rigid thick interposers and carriers for high-bandwidth and high-reliability assemblies.
What your GDS or drawing should show
A feasibility review needs five things. If you have them, the answer usually comes with a first cost indication.
Layer and polarity
Which layer is etched, and whether the drawn shape is the opening or the remaining silicon (clear or dark field).
Depth per feature
Target depth for each feature class, or "through-wafer"; the stop layer if any (buried oxide, backside film, timed).
Critical widths and tolerances
The narrowest width, the widest opening on the same layer, and the tolerance you can accept on width and depth.
Wafer stack
Substrate thickness, SOI device-layer and buried-oxide (BOX) thicknesses, films already on the wafer, and whether the backside must stay untouched.
A cross-section
One hand-drawn cross-section of the finished structure is worth more than a paragraph. Include it with your RFQ as a link or by email.
Effects we design around
Aspect-ratio dependent etching
Narrow openings etch slower than wide ones on the same wafer. We report the expected depth difference for your layout and, where needed, split the etch or adjust the layout with you.
Loading
Large open areas change the etch rate of nearby features. Dummy fill or etch order is proposed at review.
Notching on SOI
Charging at the buried oxide widens the trench foot. Etch conditions and endpoint control are selected to limit notching at the buried oxide; where a conformal liner is required, the deposition route is reviewed separately against the etched profile.
Thin wafers
Below about 300 µm the wafer is processed on a carrier or frame through etch, cleaning, and inspection; see TSV reveal for the backside flow.
Where deep etching is used
MEMS
Inertial sensors, pressure sensors, microphones, micromirrors, resonators: springs, proof masses, membranes, and release.
3D integration
TSV holes for 3D-IC and interposers, with liner, barrier, seed, fill, and reveal in the same project.
Photonics and optics
Optical access holes, fiber-alignment trenches, and cavities for hybrid integration. For crystallographic V-grooves, discuss the required profile and etching route with us.
Microfluidics and biochips
Channels, reservoirs, and through-holes in silicon, bonded to glass in the same flow.
Etched channels, bonded flow structures, and heater test chips for thermal development.
Dedicated pages that start from this process
Deep trenches lined with a dielectric and electrode stack as a process development program; values established on the first lot.
Start your project.
Initial response typically within one business day.
Share your process requirements, substrate, and production volume. A Nanosystems JP Inc. engineer will give an initial response typically within one business day. Full quote typically within 7-10 business days, subject to project complexity and NDA requirements.