Specialty Bump Services, Eutectic Die Attach & Ohmic Contacts

AuGe & AuSi Eutectic Services
361 °C / 363 °C Die Attach & Ohmic Contacts

At Nanosystems JP Inc., we deposit and pattern gold-germanium (AuGe 88/12) and gold-silicon (AuSi, typically ~97/3 wt%, commonly cited 96.8 Au / 3.2 Si) eutectics, the fluxless, high-temperature die-attach metallurgies of GaAs, SiC, and hermetic package work, and the base of the AuGe/Ni/Au ohmic contact system for n-GaAs. These eutectic compositions are typically formed by PVD evaporation rather than conventional electroplating. 4 to 12 inch wafers, from a single wafer.

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AuGe 88/12 · 361 °C AuSi ~97/3 wt% · 363 °C Stacked-layer evaporation Lift-off patterning AuGe/Ni/Au ohmic contacts Backside metallization RTA alloying in the same process flow From 1 wafer
361 °C
AuGe 88/12 eutectic -
GaAs die attach standard
363 °C
AuSi ~97/3 wt% eutectic -
classic Si die attach
4 to 12 inch
Wafer sizes supported
GaAs, SiC, InP, Si
1
Wafer minimum -
prototype to production
Thermal Hierarchy

The top of the solder ladder

AuSi 363 °C and AuGe 361 °C sit above AuSn 278 °C and indium 157 °C, so a die attached with AuGe or AuSi can be designed to stay solid through the lower-temperature reflows that follow; each assembly's thermal history is checked at engineering review.

AuSn Bump Services →
Structure After Bonding
AuGe Die Attach + Ohmic Contact
GaAs / SiC die backside metallized package header / carrier AuGe 88/12 · 361°C fluxless · fillets wet up the die edge Au plating die attach: solid through the agreed AuSn / SnAg steps below 361°C OHMIC CONTACT · n-GaAs n-GaAs AuGe Ni Au RTA alloyed · low contact R Not to scale · one metallurgy, two jobs: die attach and the n-GaAs ohmic system
Why AuGe & AuSi

Fluxless gold eutectics
for the joints that must not move

When a die must stay solid through the reflows that follow it, run hot in service, or sit in a hermetic package for long service lives, the industry reaches for gold-based eutectics. Three properties keep AuGe and AuSi irreplaceable.

Highest Practical Solder Hierarchy

Melting at 361 °C and 363 °C, AuGe and AuSi joints stay solid through AuSn attach at 278 °C, SnAg reflow around 250 °C, and every rework cycle below. That makes them the first joint in multi-step assemblies, the die attach that everything else is built on top of, and the choice for devices whose junction temperatures would creep past ordinary solders' service limits.

361 °C / 363 °C eutectics Survives AuSn & SnAg steps First joint in the stack High junction temps

Fluxless and Hermetic-Clean

Like AuSn, these gold-rich alloys bond without flux: no residue, no voiding from flux volatiles, and no cleaning chemistry inside a package that will be hermetically sealed. The joints are rigid, high-modulus, and thermally conductive, exactly what a power die or a hermetic header wants underneath it.

No flux, no residue Hermetic-package clean Rigid, conductive joint Low voiding

The n-GaAs Ohmic Contact System

AuGe is more than die attach: alloyed AuGe/Ni/Au is the standard ohmic contact to n-type GaAs, the metallization under decades of MESFETs, HEMTs, and MMICs. We deposit the stack by evaporation and lift-off and can alloy it by rapid thermal annealing in the same flow, to your contact recipe.

AuGe/Ni/Au stack n-GaAs ohmic standard Lift-off patterned RTA alloying in the same process flow
The Alloys

Evaporation-only metallurgies,
deposited as engineered stacks

Neither alloy has a practical plating chemistry, so both are built the AuSn way: alternating layers evaporated to the target composition, patterned by lift-off or deposited blanket on die backsides, homogenizing into the eutectic on the first melt.

Alloy and stack options
AuGe for GaAs, AuSi for silicon, AuGe/Ni/Au for contacts
Composition is set by layer thickness ratio at deposition. Deliverable as patterned lift-off features, blanket backside metallization, or frames, on device wafers or thinned die-attach-ready wafers.
88/12
Au:Ge wt% · EUTECTIC
Melting point: 361 °C
The GaAs die-attach standard for MMICs and hermetic microwave packages, and the base of the n-GaAs ohmic contact system. Fluxless, rigid, high-hierarchy.
97/3
Au:Si wt% · EUTECTIC
Melting point: 363 °C
The original silicon die attach. Pre-deposited AuSi controls composition instead of relying on the die to supply silicon, giving repeatable wetting and joint thickness.
Ni/Au
AuGe / Ni / Au CONTACT STACK
RTA alloyed, per your recipe
The n-GaAs ohmic workhorse under MESFETs, HEMTs, and MMICs. Lift-off patterned at ±0.5 µm; alloying by rapid thermal anneal available in the same flow.
Custom
STACKS & THICKNESSES
To your process window
Adhesion and barrier layers beneath, cap layers above, off-standard thicknesses, and frame or seal-ring geometries, engineered to your package and recipe.
Stacked-layer evaporation; composition set by layer ratio
Composition set by layer thickness ratio
Lift-off patterning at ±0.5 µm, or blanket backside deposition
Die-attach layers 1 to 5 µm typical; ohmic stacks 0.1 to 0.3 µm typical
Thinned-wafer backside processing available
RTA alloying for ohmic contacts available in flow
Seal frames and preform-replacement pads on request
From 1 wafer; repeat lots on an established baseline recipe
Full Process Flow
Litho to Die Attach
1 · Resist coat on UBM-finished wafer 2 · Expose · develop undercut profile 3 · Evaporate full stack · one vacuum 4 · Lift-off resist + field metal gone 5 · Eutectic melt homogenizes on first melt 6 · Die attach fluxless, at 361/363 °C →→→→→ Not to scale · stacked Au/Ge or Au/Si layers · composition by layer ratio
Process Specifications

Complete AuGe / AuSi
fabrication parameters

ParameterAuGe (88/12)AuSi (97/3)
Eutectic Temperature361 °C363 °C
Wafer Sizes4 to 12 inch (100 to 300 mm)
SubstratesGaAs, Si, SiC, InP; others on request
DepositionStacked-layer evaporation; composition by layer thickness ratio
PatterningLift-off (±0.5 µm) or blanket backside
Die-Attach Layer Thickness1 to 5 µm typical
Ohmic Contact StackAuGe/Ni/Au, 0.1 to 0.3 µm typicalN/A
RTA AlloyingAvailable in flow, per recipeN/A
Composition ControlLayer thickness ratio at deposition
Backside ProcessingThinned-wafer handling available
InspectionProfilometry + SEM standard; cross-section on request
Minimum LotFrom 1 wafer; R&D runs to repeat lots on one baseline recipe
Eutectic Temperatures on One Scale
Thermal Hierarchy Ladder
400°C300°C200°C100°C25°C Al-Ge · 424°C AuSi ~97/3 wt% · 363°C AuGe 88/12 · 361°C 97Pb/3Sn · ~320°C 95Pb/5Sn · ~310°C AuSn 80/20 · 278°C In50Pb50 · liq. ~209°C Indium · 157°C In-3Ag · 143°C Bi58Sn42 · 139°C In52Sn48 · 118°C Au bumps · solid-state · no melt step at all step-solder upward: each joint stays solid through the agreed lower steps One flow covers the whole ladder · all evaporated + lift-off except plated Au / AuSn / Cu-Sn options
Applications

AuGe and AuSi across GaAs,
SiC, and hermetic packaging

GaAs MMIC Die Attach

AuGe die attach for GaAs power amplifiers and MMICs in telecom, radar, and satellite hardware, the fluxless, high-hierarchy joint that hermetic microwave packages are built on, with thermal conduction the die's dissipation depends on.

GaAs PA · MMIC · Radar · Satellite · Hermetic microwave

n-GaAs Ohmic Contacts

Alloyed AuGe/Ni/Au ohmic contacts for MESFET, HEMT, and MMIC front-ends, evaporated, lift-off patterned, and RTA alloyed to your recipe, with the low, stable contact resistance decades of III-V manufacturing established.

MESFET · HEMT · MMIC · RTA alloyed · Low contact R

SiC & High-Temperature Power

Gold-eutectic die attach for SiC and other wide-bandgap devices whose junction temperatures overrun ordinary solders, keeping the joint solid and conductive where the device actually operates.

SiC · Wide bandgap · High Tj · Traction & industrial

Hermetic Headers & TO Packages

AuSi and AuGe attach into hermetic headers, TO cans, and ceramic packages, fluxless joints with no flux residues or polymer dielectrics in the joint, in the package styles that space, defense, and sensing programs still qualify.

TO cans · Ceramic packages · Headers · No retained flux or polymer

Laser & LED Bar Attach

High-hierarchy eutectic attach for laser bars and LED arrays where subsequent AuSn or solder steps follow, the first, hottest joint in a multi-metallurgy optical assembly.

Laser bars · LED arrays · Multi-step assembly · First joint

Hi-Rel Space & Defense

Gold-eutectic joints carry decades of qualification heritage in space and defense hardware. We support new builds and legacy-process reproduction from single-wafer lots with full process documentation.

Space heritage · Defense hi-rel · Legacy reproduction · Documented
Anatomy of an AuGe Attach · Cross-Section
header / carrier / package basedieAu / Ge layers · eutectic ratiodie backside metallizeddie-attach interfacefirst melt 361 °CWhole stack homogenizes at first melt, then freezes as one alloyAuSi variant 363 °C · Not to scale
Why Nanosystems JP Inc.

What makes our AuGe / AuSi capability
different

01

The AuSn playbook, applied

Stacked-layer evaporation, layer-ratio composition control, lift-off patterning: the discipline proven on our AuSn flow runs these alloys the same way.

02

Die attach and ohmic in one flow

Backside die-attach metallization and front-side AuGe/Ni/Au contacts, with RTA alloying, run as one program instead of two separate procurements.

03

Evaporation-only alloys, done properly

These metallurgies cannot be plated, and services built around plating avoid them. Evaporation and lift-off are the standard route for this service, so AuGe and AuSi are standard work, not exceptions.

04

Thermal hierarchy engineered

We ask what comes after this joint, AuSn, SnAg, rework, and place your attach at the right rung of the ladder, with the companion metallurgies available on the same UBM.

05

Compound-substrate handling

GaAs and InP wafers, thinned backsides, and fragile die-attach-ready substrates are handled with adapted chucking and thermal budgets, the routine case in this application space.

06

From 1 wafer, no minimum lot

Prototype on a single wafer, verify composition and wetting, then scale on the same recipe with the prototype data as baseline. That prototype data becomes the baseline for repeat production.

Related service

Annealing: The rapid thermal annealing behind AuGe/Ni/Au ohmic alloying, N₂, H₂, vacuum, and RTA, is its own service for every contact and activation step in your flow.

Annealing →

Start your project.
Initial response typically within one business day.

Share your process requirements, substrate, and production volume. A Nanosystems JP Inc. engineer will give an initial response typically within one business day. Full quote typically within 7-10 business days, subject to project complexity and NDA requirements.

To speed up technical review, please include:
substrate type & size  ·  target process  ·  quantity  ·  timeline  ·  design files if available (not required for first review)

sales@nanosystemsjp.co.jp · +81-3-5288-5569 · NDA available on request

Ready to discuss this process?
Initial engineering response: typically within one business day. NDA available.
Request a Quote →
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Capabilities Overview
Substrates
Substrate & WafersSi, SiC, GaN, glass, sapphire Fused Silica WafersQuartz · borosilicate · low CTE Glass ProcessingDrilling, etching, polishing PI Film & SUS Sensor FabRoll-to-roll · sensor patterning
Front-End
Mask FabricationGDS to chrome mask, DRC PhotolithographyE-beam 20 nm to 500 × 600 mm NanoimprintingUV & thermal NIL Thin Film DepositionPVD, CVD, ALD, MBE ALD CoatingConformal oxides, nitrides PECVD DielectricsSiO₂, SiN, SiON, a-Si TFT & BackplaneIGZO · Glass · Display Lift-OffMetal pattern · shadow mask ElectroplatingCu TSV fill, DPC, LIGA Electroforming & LIGANi shims, meshes, microstructures EtchingICP-RIE, DRIE >50:1 ICP-RIE EtchingSi, oxide, III-V, SiC, quartz MEMS FoundrySensors, actuators, microfluidics Microchannel CoolingEtched, bonded, heater test chips Thermal Test ChipsHeater dies, multi-zone, RTD Temperature SensorsPt/NiCr RTDs, thermocouples AnnealingN₂ / H₂ / vacuum / RTA Ion ImplantationB / P / As / Al / N implant CMP & GrindingCu CMP, 50 µm thinning Wafer ThinningTo 50 µm on carriers Backside MetallizationTi/Ni/Ag, Ti/Ni/Au, Ti/Cu Patterned Test WafersCustom CMP and process evaluation wafers Daisy-Chain Test DiesDummy dies, chains, bump options DicingBlade, stealth laser Stealth & Laser Dicing300 mm Si and glass, SDBG Wafer CleaningRCA, plasma, megasonic Cleaning ChemistryPiranha, SC-1, SC-2, RCA
Advanced Packaging
Wafer BondingHybrid, eutectic, fusion Anodic BondingGlass to silicon, cavities MEMS Cap WafersCavities, ports, seal lands, bonded TSV FabricationHigh AR, Cu fill InterposersSi and glass, TSV/TGV + RDL TSV RevealBackgrind → etch → CMP TGV FabricationThrough-glass via Glass TGV CouponsHole-only to routed prototypes RDL FabricationBCB / PBO / PI + damascene Packaging & AssemblyWire bond, flip-chip Flip-Chip BondingTC, reflow, AuSn, underfill 3D / 2.5D PackagingTSV + RDL + UBM + C4 AuSn BumpPVD lift-off, fluxless Laser SubmountsSi/AlN submounts, optical benches Indium BumpEvap lift-off · cryo/quantum UBM DepositionTi/Pt/Au · adhesion-barrier-Au Cu Pillar & SnAg BumpingPillars with SnAg caps, SnAg bumps Gold BumpEvap & plated · Au-Au TC AuGe / AuSi361/363 °C eutectic die attach High-Pb Bumps95Pb5Sn · hi-rel C4 SLID / TLPCu/Sn · Au/In · Ag/In Al-Ge Sealing424 °C · CMOS-friendly MEMS Ohmic ContactsGaAs · GaN · RTA + TLM SiC ProcessingContacts, implant, 1800 °C anneal GaN & III-VGaN, GaAs, InP processing Cryo / UHV MetalAuSn · Ti/Pd/Au · rings Optical AccessWindows · meshes · holes Vapor CellsDRIE + bond · unfilled TFOI WafersQuartz-on-Si · LNOI Biochip & MicrofluidicsGlass 500 × 600 mm, NIL SiPho PackagingTSV · RDL · UBM · C4 for PIC Photonic DevicesSiN/SOI waveguides, gratings
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