Wafer Metallization
and PVD Coating Services
Wafer metallization by sputtering, e-beam and thermal evaporation, electroplating, and electroless plating, with ALD barrier and liner options for process integration: adhesion layers, barriers, seeds, UBM, ohmic contacts, bump metals, and thick copper. Supported substrate sizes and film stacks depend on the selected process. Send your film stack for an initial engineering response typically within one business day.
alloys
diameters
sputter, evap, PECVD
order
Metals and alloys
UBM stacks
Ti/Ni/Au, Ti/Pt/Au, TiW/Au, Cr/Cu/Au for solder and gold bumping; electroless Ni/Au and Ni/Pd/Au where current cannot be applied. UBM deposition
Ohmic and Schottky contacts
Ti/Al/Ni/Au on GaN, Ni-based on SiC, AuGe/Ni/Au on GaAs, with alloying and RTA in the same project; contact behavior depends on the semiconductor, doping, surface preparation, stack, and thermal processing. Ohmic contacts
Barrier and seed for Cu
Ta/TaN or TiN barrier with sputtered Cu seed for TSV, TGV, and damascene RDL. RDL fabrication
Bump metals
Au, AuSn multilayers, SnAg, high-Pb, and indium bump metallization, with deposition and patterning routes selected for the required stack. Gold · AuSn · Indium
Cryogenic and UHV stacks
All-metal, fluxless stacks for quantum, cryogenic, and vacuum devices. Cryogenic and UHV metallization
Optical and functional coatings
Reflective and absorber metals, transparent conductors (ITO), and multilayer stacks for photonics and displays. Thin film deposition
Wafer Metallization and PVD Coating Services
Scope and specification options. Every figure is confirmed for your program in the quotation.
How the metal is patterned
Tell us the pattern route you prefer, or describe the geometry and we propose one.
| Route | How it works | Typical use |
|---|---|---|
| Blanket deposition | Unpatterned full-wafer deposition; inspection items and sampling are agreed for each project | Seed layers, backside metal, test wafers |
| Lift-off | Resist pattern first, evaporation, then resist strip lifts the field metal | Noble metals and multilayers that are hard to etch: Pt, Au, AuSn, In |
| Subtractive metal patterning | Deposit the blanket metal film, define the resist pattern, etch the exposed metal, and remove the resist | Al, Cu, Ti, W, and where fine lines with straight edges are needed |
| Plating through resist | Seed layer, thick resist pattern, electroplating in the openings, strip, seed etch | Bumps, pillars, RDL, thick Cu and Ni |
| Shadow mask | Metal mask held on the wafer during PVD | Coarse features on fragile devices; no resist contact. Mask fabrication |
What we coat
Wafers
Si and SOI 2-12-inch, SiC, GaN-on-Si, GaAs, InP, sapphire, glass and fused silica, LiNbO₃ and other piezoelectrics; thin wafers on carriers.
Panels and sheets
Glass and polymer panels to 500 × 600 mm for sputtering, evaporation, and PECVD (not every material, film, or fixture; confirmed per program); polyimide and stainless foils for flexible devices.
Pieces and devices
Coupons, diced chips, and finished devices for evaluation, with fixturing adapted to the part.
Ceramics
AlN and Al₂O₃ with sputtered adhesion layers for DPC copper on power modules.
Metallization and supporting deposition methods
Each method is described in full on the thin film deposition page. This table is the short version, for choosing between them in a metal stack.
Each method suits a thickness range and a purpose. Most stacks combine two: a sputtered or evaporated adhesion and seed stack, then electroplated thickness where microns are needed.
Schematic; layers and thicknesses are set per program.
Adhesion, barrier, seed, then thickness
Most metal interconnects start with thin sputtered or evaporated adhesion and barrier layers and add thickness by electroplating where microns are needed. Each layer is chosen for the substrate, the thermal history that follows, and what the finish must do: solder wetting, wire bonding, low contact resistance.
| Method | Typical thickness | Best for | Detail page |
|---|---|---|---|
| Sputtering (PVD) | 10 nm to 2 µm | Adhesion, barrier, seed, and alloy layers; uniform blanket films on wafers and panels | Thin film deposition |
| E-beam and thermal evaporation | 10 nm to 1 µm | Lift-off patterned metals (Ti, Cr, Ni, Pt, Au, Al, In, AuSn multilayers), directional deposition | Lift-off patterning |
| ALD | 1 to 50 nm | Conformal barrier and dielectric liners in high-aspect-ratio features | Thin film deposition |
| Electroplating | 1 to 100 µm | Thick Cu, Ni, Au, SnAg, and indium: TSV fill, RDL, pillars, bumps, LIGA | Electroplating |
| Electroless plating | 0.1 to 10 µm | ENIG and ENEPIG finishes on compatible, appropriately prepared metal pads; no external plating current is required | Electroplating |
For a film-stack review
A process engineer gives an initial response typically within one business day and proposes the method per layer after review. How ordering works →
Check a thermal budget
Enter your device's maximum temperature to see which processes fit. Typical windows: evaporation and sputtering with lift-off 20 to 150 °C; PVD AuSn and solder metals to 150 °C; ALD 80 to 300 °C; PECVD 150 to 400 °C; AuSn eutectic ~280 °C; AuSi ~363 °C; Al-Ge ~424 °C; anodic bonding 300 to 450 °C; thermal oxidation 900 to 1100 °C; SiC implant activation 1400 to 1800 °C. Confirmed per program.
Start your project.
Initial response typically within one business day.
Share your process requirements, substrate, and production volume. A Nanosystems JP Inc. engineer will give an initial response typically within one business day. Full quote typically within 7-10 business days, subject to project complexity and NDA requirements.