Cryogenic & UHV
Assembly Metallization
At Nanosystems JP Inc., we deposit and pattern the metallization that vacuum cans and cryostats will tolerate: fluxless AuSn multilayer PVD for in-vacuum die attach, Ti/Pd/Au and Ti/Pt/Au stacks for wire-bondable, solder-wettable surfaces, and low-outgassing seal rings, all-metal, no organics, no flux, patterned by lift-off at ±0.5 µm. On your wafers or on metallized AlN and SiC carriers, from a single wafer, managed end to end by a dedicated project manager.
in the joint stack
compatible with typical post-bond vacuum bake-outs
for pads, rings, traces
research-lot native
The reflow-oven assumptions do not survive a vacuum can
Standard assembly metallurgy assumes flux, polymers, and air. UHV and cryogenic assemblies put hard limits on flux residues, organics, trapped volatiles, and outgassing, which is exactly why all-metal, fluxless joining is attractive at critical interfaces. Our AuSn flow already lives by those rules; this page is that discipline packaged for vacuum and cryostat builders, with indium as the companion service where compliance at 4K matters more than rigidity.
No flux residues or polymer dielectrics in the joint stack,
metallurgies chosen to tolerate 4 K excursions
Three rules govern metallization that goes into vacuum or cold, and each one is a deposition decision, made before your assembly ever sees a chamber.
The Low-Outgassing Metallurgy Class
Every layer we put down for this service is metal: AuSn, Ti, Pd, Pt, Au. No flux ever touches the joint and no polymer enters the stack. Residual-organic cleanliness is verified to the agreed criterion before bake-out. Evaporated AuSn bonds fluxlessly in vacuum or forming gas, which is exactly why it is the metallurgy class UHV instrument builders specify by habit.
Chosen for Cold, Not Just Clean
Cryogenic cycling punishes the wrong joint. We keep both answers on one flow: rigid, hermetic AuSn where the assembly is CTE-matched and bake-out follows, and compliant indium from the companion bump service where repeated 300K-to-4K cycling demands a joint that deforms instead of cracking. Carrier choices, AlN and SiC, are made for the thermal path at operating temperature.
Patterned, Not Painted
Vacuum hardware wants metal exactly where designed and nowhere else: bond pads that match die, seal rings that match lids, traces that dodge optical and beam paths. Lift-off gives all of it at ±0.5 µm, double-side where feedthroughs and windows demand, with the stack deposited in one pump-down so no interface ever sees air.
The stack, the ring,
and the flow
What lands on your carrier, what a seal ring looks like from above, and the four steps between bare substrate and a fluxless bond.
AuSn, Ti/Pd/Au, seal rings,
and metallized carriers
Four deliverable families, deposited on your wafers, your machined parts where geometry allows, or on carrier substrates we supply.
Complete cryo / UHV metallization
parameters
| Parameter | Specification |
|---|---|
| Die-Attach Metallurgy | AuSn multilayer PVD, fluxless; eutectic 278 °C; indium alternative via bump line |
| Surface Stacks | Ti/Pd/Au, Ti/Pt/Au, Ti/Au; adhesion-barrier-noble sequences per program |
| Seal Rings | AuSn, Au (thermocompression), SLID couples; widths from ~20 µm |
| Organics in Stack | None; all-metal, fluxless, polymer-free |
| Wafer Sizes | 4 to 12 inch (100 to 300 mm); pieces and carriers per drawing |
| Substrates | Si, glass, fused silica, sapphire, AlN, SiC; others on request |
| Patterning | Lift-off, ±0.5 µm; double-side alignment available |
| Deposition | E-beam / thermal evaporation, one pump-down, in-situ pre-clean |
| Carrier Deliverables | Metallized, patterned, and diced AlN / SiC submounts to drawing |
| Metrology | Per program; SEM and cross-section on request |
| Minimum Lot | From 1 wafer; R&D runs to repeat lots on one baseline recipe |
Where vacuum and cold
set the rules
Ion Trap Assembly
Fluxless AuSn attach for trap die on carriers inside the vacuum can, with Ti/Pd/Au pads and routing patterned to keep laser paths clear, nothing organic anywhere near the trap.
Cryostat Stages & Submounts
Metallized AlN and SiC submounts for 4K stages: die-attach lands, thermal paths, and wire-bond surfaces that survive cooldown cycling without delamination or creep surprises.
Cryogenic Detector Assemblies
Attach and interface metallization for cooled detector and sensor assemblies, paired with the indium bump line when the detector side calls for compliant, superconducting-friendly joints.
UHV Instrument Hardware
Pads, seal rings, and bondable surfaces for surface-science, beam-line, and analytical instruments, where a single fingerprint of flux can dominate the residual gas spectrum.
Photonics in the Cold
AuSn-attached photonic die and metallized optical carriers for cryogenic photonics and transduction experiments, on the same flow as our photonics bump services.
R&D Hardware Batches
Single carriers, small submount batches, and one-off metallized parts for experiment builds, quoted from a drawing, delivered ready for your bonder.
What makes our cryo / UHV capability
different
AuSn is established practice
The AuSn multilayer flow developed for photonics programs is applied here to the needs of vacuum and cryostat builders.
Both joint philosophies
Rigid, hermetic-capable AuSn and compliant indium are both offered, and the recommendation is made per assembly rather than by habit.
Clean by construction
No flux and no organics is not a cleaning step here, it is the process design: all-metal stacks, fluxless bonds, no retained flux or polymer in the joint; bakeout and residual-gas needs are agreed per program.
Carriers included
AlN and SiC submounts metallized, patterned, and diced under the same program, so the thermal path arrives finished, not as a sourcing project.
Research-lot native
Single wafers, single carriers, one-off parts to drawing: the lot sizes experiment builders actually need.
One program, one manager
Metallization, carriers, and the neighboring bump and bonding services run as one thread, managed end to end by a dedicated project manager.
Start your project.
Initial response typically within one business day.
Share your process requirements, substrate, and production volume. A Nanosystems JP Inc. engineer will give an initial response typically within one business day. Full quote typically within 7-10 business days, subject to project complexity and NDA requirements.