At Nanosystems JP Inc., we deposit and pattern the metallization that vacuum cans and cryostats allow: fluxless AuSn multilayer PVD for in-vacuum die attach, Ti/Pd/Au and Ti/Pt/Au stacks for wire-bondable, solder-wettable surfaces, and low-outgassing seal rings, all-metal, no organics, no flux, patterned by lift-off at ±0.5µm. On your wafers or on metallized AlN and SiC carriers, from a single wafer, managed end to end by a dedicated project manager.
The reflow-oven assumptions do not survive a vacuum can
Standard assembly metallurgy assumes flux, polymers, and air. UHV and cryogenic hardware forbid all three, so the metallization has to be rethought from the stack up. Our AuSn flow already lives by those rules; this page is that discipline packaged for vacuum and cryostat builders, with indium next door where compliance at 4K matters more than rigidity.
Three rules govern metallization that goes into vacuum or cold, and each one is a deposition decision, made before your assembly ever sees a chamber.
Every layer we put down for this service is metal: AuSn, Ti, Pd, Pt, Au. No flux ever touches the joint, no polymer enters the stack, no organic residue waits to desorb during bake-out. Evaporated AuSn bonds fluxlessly in vacuum or forming gas, which is exactly why it is the metallurgy class UHV instrument builders specify by habit.
Cryogenic cycling punishes the wrong joint. We keep both answers on one flow: rigid, hermetic AuSn where the assembly is CTE-matched and bake-out follows, and compliant indium from the adjacent bump line where repeated 300K-to-4K cycling demands a joint that deforms instead of cracking. Carrier choices, AlN and SiC, keep the thermal path honest at temperature.
Vacuum hardware wants metal exactly where designed and nowhere else: bond pads that match die, seal rings that match lids, traces that dodge optical and beam paths. Lift-off gives all of it at ±0.5µm, double-side where feedthroughs and windows demand, with the stack deposited in one pump-down so no interface ever sees air.
What lands on your carrier, what a seal ring looks like from above, and the four steps between bare substrate and a fluxless bond.
Four deliverable families, deposited on your wafers, your machined parts where geometry allows, or on carrier substrates we supply.
| Parameter | Specification |
|---|---|
| Die-Attach Metallurgy | AuSn multilayer PVD, fluxless; eutectic 278°C; indium alternative via bump line |
| Surface Stacks | Ti/Pd/Au, Ti/Pt/Au, Ti/Au; adhesion-barrier-noble sequences per program |
| Seal Rings | AuSn, Au (thermocompression), SLID couples; widths from ~20µm |
| Organics in Stack | None; all-metal, fluxless, polymer-free |
| Wafer Sizes | 4 inch (100mm), 6 inch (150mm), 8 inch (200mm); pieces and carriers per drawing |
| Substrates | Si, glass, fused silica, sapphire, AlN, SiC; others on request |
| Patterning | Lift-off, ±0.5µm; double-side alignment available |
| Deposition | E-beam / thermal evaporation, one pump-down, in-situ pre-clean |
| Carrier Deliverables | Metallized, patterned, and diced AlN / SiC submounts to drawing |
| Metrology | Per program; SEM and cross-section on request |
| Minimum Lot | From 1 wafer, prototype to repeat lots on the same recipe |
Fluxless AuSn attach for trap die on carriers inside the vacuum can, with Ti/Pd/Au pads and routing patterned to keep laser paths clear, nothing organic anywhere near the trap.
Metallized AlN and SiC submounts for 4K stages: die-attach lands, thermal paths, and wire-bond surfaces that survive cooldown cycling without delamination or creep surprises.
Attach and interface metallization for cooled detector and sensor assemblies, paired with the indium bump line when the detector side calls for compliant, superconducting-friendly joints.
Pads, seal rings, and bondable surfaces for surface-science, beam-line, and analytical instruments, where a single fingerprint of flux can dominate the residual gas spectrum.
AuSn-attached photonic die and metallized optical carriers for cryogenic photonics and transduction experiments, on the same flow as our photonics bump services.
Single carriers, small submount batches, and one-off metallized parts for experiment builds, quoted from a drawing, delivered ready for your bonder.
Our AuSn multilayer flow already serves photonics programs daily; this service is that proven discipline aimed at vacuum and cryostat builders.
Rigid hermetic AuSn and compliant indium on adjacent lines, recommended per assembly, not per what we happen to run.
No flux and no organics is not a cleaning step here, it is the process design: all-metal stacks, fluxless bonds, nothing to remove.
AlN and SiC submounts metallized, patterned, and diced under the same program, so the thermal path arrives finished, not as a sourcing project.
Single wafers, single carriers, one-off parts to drawing: the lot sizes experiment builders actually need, without apology.
Metallization, carriers, and the neighboring bump and bonding services run as one thread, managed end to end by a dedicated project manager.
Share your process requirements, substrate, and production volume. A Nanosystems JP Inc. engineer will respond within 24 hours. Full quote typically within 7-10 business days, subject to project complexity and NDA requirements.