At Nanosystems JP Inc., we deposit and pattern the aluminum and germanium layers behind Al-Ge eutectic wafer bonding: the gold-free, CMOS-compatible metallurgy that seals inertial MEMS cavities in volume production. Ge patterned by lift-off over Al, or the reverse, because etching germanium selectively over aluminum is a fight nobody should pick. 424°C eutectic, seal frames and electrical interconnect in the same layer, cap and device wafers processed as a pair. From a single wafer pair.
The eutectic a CMOS fab will actually allow
AuSn and AuSi seal beautifully, but gold is contamination poison on CMOS lines. Aluminum is already the fab's own metal and germanium is benign, which is why Al-Ge became the volume metallurgy for MEMS-on-CMOS cavity sealing. For gold-permitted packages, AuSn and SLID frames remain the companions on the same flow.
Three properties made Al-Ge the production standard for inertial MEMS sealing, and the third one is exactly why the layers come to us.
Aluminum is the standard interconnect metal of every CMOS line and germanium carries none of gold's contamination stigma, so Al-Ge sealing passes fab review where Au-bearing eutectics are banned outright. That single fact put Al-Ge inside high-volume gyroscopes and accelerometers, MEMS sealed directly over their readout circuits.
The bonded eutectic is metallic and conductive, so the same layer that hermetically closes the cavity also carries electrical interconnect and ground between cap and device wafer. One deposition, one bond, two functions, and at 424°C the joint then shrugs off every downstream solder, mold, and reflow step in the assembly.
Patterning germanium by etch means finding chemistry that eats Ge while sparing the aluminum right beneath it, an unpleasant selectivity problem with real yield consequences. Lift-off sidesteps it entirely: the Ge lands only where the resist opening allows, the Al underneath is never exposed to an etchant, and frame edges are resist-defined at ±0.5µm. That is why Ge-over-Al lift-off is the common route, and it is our native discipline.
The bond needs aluminum on one surface meeting germanium on the other, or the full couple pre-built on one side. We deposit whichever split your integration demands, on cap wafers, device wafers, or both.
| Parameter | Specification |
|---|---|
| Eutectic Temperature | 424°C (Al-Ge eutectic) |
| Wafer Sizes | 4 inch (100mm), 6 inch (150mm), 8 inch (200mm), 12 inch (300mm) |
| Substrates | Si, MEMS device wafers, CMOS cap wafers; others on request |
| Layer Thicknesses | Al 0.3-1µm, Ge 0.2-0.6µm typical, tuned per bond recipe |
| Configurations | Ge-on-Al, Al-on-Ge, split across wafer pair |
| Patterning | Lift-off, ±0.5µm registration; blanket available |
| Frame Width | From ~20µm |
| Additional Features | Interconnect, pads, and ground paths in the seal layer |
| Metrology | Documented per lot; SEM on request |
| Bonding | At your line; trials via our wafer bonding service |
| Minimum Lot | From 1 wafer pair, prototype to production on the same recipe |
The flagship application: hermetic cavity sealing for inertial MEMS at consumer and automotive volume, gold-free over CMOS readout, with the vacuum level the resonating structures demand held for the product's life.
Vacuum-sealed cavities for MEMS oscillators and timing references, where cavity pressure sets Q factor and the seal must be conductive, stable, and reflow-proof through packaging.
Reference-cavity sealing for absolute pressure sensors and protected environments for environmental sensing elements, with electrical feedthrough landings in the same layer.
Vacuum packaging for thermal imaging arrays, where cavity vacuum is the sensitivity budget and a gold-free, wafer-level seal keeps the process CMOS-compatible.
Cap wafers as a deliverable: cavity-etched, Al-Ge framed, ready to bond onto your device wafers, drawing on our DRIE and lithography flow for the cavity side.
Single matched pairs for bond development: thickness-ratio splits, frame geometry variants, and bond trials through our wafer bonding service to converge on your recipe.
Ge-over-Al selectivity is the known pain of this metallurgy, and lift-off is the known answer. It happens to be the discipline our entire bump family runs on.
Cap and device sides deposited, patterned, and documented together, so the couple meets at bond exactly as designed.
DRIE cavities, lithography, deposition, and lift-off run as one flow, managed end to end by a dedicated project manager, cap wafers arrive finished, not as a relay race.
Al:Ge thickness ratio, frame width, and force budget are set to your bond recipe and documented, not copied from a paper.
Al-Ge for gold-free CMOS work, AuSn and SLID frames where gold is allowed, all patterned on the same line, so the metallurgy fits the fab rules, not the reverse.
Prototype the seal on a single pair, bond, leak-test at your line, then scale on the same recipe. No re-qualification required.
Share your process requirements, substrate, and production volume. A Nanosystems JP Inc. engineer will respond within 24 hours. Full quote typically within 7-10 business days, subject to project complexity and NDA requirements.