Al-Ge Eutectic Bonding Layers
424 °C Hermetic MEMS Sealing
At Nanosystems JP Inc., we deposit and pattern the aluminum and germanium layers behind Al-Ge eutectic wafer bonding: the gold-free, CMOS-compatible metallurgy that seals inertial MEMS cavities in volume production. Ge patterned by lift-off over Al, or the reverse, because etching germanium selectively over aluminum is impractical. 424 °C eutectic, seal frames and electrical interconnect in the same layer, cap and device wafers processed as a pair. From a single wafer pair.
qualified for the agreed downstream sequence
suited to CMOS/MEMS integration
lift-off defined
prototype to production
A gold-free eutectic for CMOS and MEMS lines
AuSn and AuSi seal beautifully, but gold is contamination poison on CMOS lines. Aluminum is already the fab's own metal and germanium integrates without adding Au contamination, which is why Al-Ge became the volume metallurgy for MEMS-on-CMOS cavity sealing. For gold-permitted packages, AuSn and SLID frames remain the companions on the same flow.
Gold-free, conductive,
with Ge etch selectivity managed by design
Three properties made Al-Ge the production standard for inertial MEMS sealing, and the third one is exactly why the layers come to us.
CMOS-Fab-Friendly Chemistry
Aluminum is a familiar CMOS metallization and germanium carries none of gold's contamination stigma, so Al-Ge avoids the Au-contamination concerns that can restrict gold-bearing bonding metallurgies in CMOS-compatible process environments. That single fact put Al-Ge inside high-volume gyroscopes and accelerometers, MEMS sealed directly over their readout circuits.
Seal and Contact in One Layer
The bonded eutectic is metallic and conductive, so the same layer that hermetically closes the cavity also carries electrical interconnect and ground between cap and device wafer. One deposition, one bond, two functions, and at 424 °C the joint remains solid through downstream solder, mold, and reflow steps in the assembly.
Lift-Off Beats the Ge Etch
Patterning germanium by etch means finding chemistry that eats Ge while sparing the aluminum right beneath it, an unpleasant selectivity problem with real yield consequences. Lift-off sidesteps it entirely: the Ge lands only where the resist opening allows, the Al underneath is never exposed to an etchant, and frame edges are resist-defined at ±0.5 µm. That is why Ge-over-Al lift-off is the common route, and it is our native discipline.
Ge over Al, Al over Ge,
and both wafers of the pair
The bond needs aluminum on one surface meeting germanium on the other, or the full couple pre-built on one side. We deposit whichever split your integration demands, on cap wafers, device wafers, or both.
Complete Al-Ge layer
parameters
| Parameter | Specification |
|---|---|
| Eutectic Temperature | 424 °C (Al-Ge eutectic) |
| Wafer Sizes | 4 to 12 inch (100 to 300 mm) |
| Substrates | Si, MEMS device wafers, CMOS cap wafers; others on request |
| Layer Thicknesses | Al 0.3 to 1 µm, Ge 0.2 to 0.6 µm typical, tuned per bond recipe |
| Configurations | Ge-on-Al, Al-on-Ge, split across wafer pair |
| Patterning | Lift-off, ±0.5 µm registration; blanket available |
| Frame Width | From ~20 µm |
| Additional Features | Interconnect, pads, and ground paths in the seal layer |
| Metrology | Documented per lot; SEM on request |
| Bonding | At your line; trials via our wafer bonding service |
| Minimum Lot | From 1 wafer pair; R&D runs to repeat lots on one baseline recipe |
Al-Ge across inertial MEMS
and vacuum packaging
Gyroscopes & Accelerometers
The flagship application: hermetic cavity sealing for inertial MEMS at consumer and automotive volume, gold-free over CMOS readout, with the vacuum level the resonating structures demand held for the product's life.
MEMS Resonators & Timing
Vacuum-sealed cavities for MEMS oscillators and timing references, where cavity pressure sets Q factor and the seal must be conductive, stable, and reflow-proof through packaging.
Pressure & Environmental Sensors
Reference-cavity sealing for absolute pressure sensors and protected environments for environmental sensing elements, with electrical feedthrough landings in the same layer.
Microbolometers & IR
Vacuum packaging for thermal imaging arrays, where cavity vacuum is the sensitivity budget and a gold-free, wafer-level seal keeps the process CMOS-compatible.
Cap Wafer Fabrication
Cap wafers as a deliverable: cavity-etched, Al-Ge framed, ready to bond onto your device wafers, drawing on our DRIE and lithography flow for the cavity side.
R&D Wafer Pairs
Single matched pairs for bond development: thickness-ratio splits, frame geometry variants, and bond trials through our wafer bonding service to converge on your recipe.
What makes our Al-Ge capability
different
Lift-off where etch fails
Ge-over-Al selectivity is the known pain of this metallurgy, and lift-off is the known answer. It happens to be the discipline our entire bump family runs on.
Both wafers, one flow
Cap and device sides deposited, patterned, and documented together, so the couple meets at bond exactly as designed.
Cavity to frame under one program
DRIE cavities, lithography, deposition, and lift-off run as one flow, managed end to end by a dedicated project manager, so cap wafers arrive finished rather than as a sequence of separately ordered steps.
Ratio engineered to your bonder
Al:Ge thickness ratio, frame width, and force budget are set to your bond recipe and documented, not copied from a paper.
The whole seal-frame menu
Al-Ge for gold-free CMOS work, AuSn and SLID frames where gold is allowed, all available in one project, so the metallurgy fits the fab rules, not the reverse.
From 1 pair, no minimum lot
Prototype the seal on a single pair, bond, leak-test at your line, then scale on the same recipe. That prototype data becomes the baseline for repeat production.
Start your project.
Initial response typically within one business day.
Share your process requirements, substrate, and production volume. A Nanosystems JP Inc. engineer will give an initial response typically within one business day. Full quote typically within 7-10 business days, subject to project complexity and NDA requirements.