At Nanosystems JP Inc., we build engineered substrates that almost nobody will run in small lots: crystalline quartz bonded to silicon below 570°C, lithium niobate on insulator, and piezoelectric films on Si or sapphire carriers. The flow is composed from capabilities this site already documents, fusion and plasma-activated bonding, grinding and CMP thinning toward 50µm and below, and the substrate program that sources the crystals, and the entire page is framed around what it really is: 3-5 wafer prototype lots, delivered with data, for teams whose device idea starts with a substrate that does not exist yet.
Volume suppliers of engineered substrates start at volumes
Established engineered-substrate makers quote in the hundreds of wafers; a research team needs four. That gap is where device programs die, and it is exactly the gap our bonding, grinding and CMP, and substrate programs were built to close, one small, well-documented lot at a time.
Every stack on this page is the same three-act play performed with different crystals, and each act is a documented capability of this line.
Fusion and plasma-activated bonding join the functional crystal to its carrier at temperatures the crystal dictates, for quartz-on-Si that means staying below 573°C, the α-β transition, which our low-temperature plasma-activated route respects with margin. Interlayer oxides, and metal or adhesive couples where a stack demands them, come from the same bonding service.
The bonded crystal starts as a full-thickness wafer and ends as a film: grinding takes the bulk, CMP takes the damage, and the flow that thins device wafers toward 50µm carries the same stack thickness control here. Target thickness and uniformity are set per program against your device physics, resonator, waveguide, or transducer.
CMP finishing below 0.5nm Ra gives the film a device-ready surface, and metrology closes the loop: thickness maps, TTV, and roughness shipped with every lot, because a prototype substrate without data is a rumor. Downstream patterning, metallization, and dicing continue on the same line when your program wants the device, not just the wafer.
The three acts of every TFOI stack, drawn once: full-thickness crystal down to a measured film.
Four stack families, all quoted at 3-5 wafer prototype lots, with the crystal sourcing handled through our substrate program so one order covers material and process.
| Parameter | Specification |
|---|---|
| Stack Families | Quartz-on-Si, LNOI, piezo-on-carrier (bonded or deposited AlN / PZT), custom per feasibility |
| Carriers | Si standard; sapphire and others per program via the substrate program |
| Bonding | Fusion, plasma-activated; oxide interlayers; metal / adhesive couples per stack |
| Thermal Budget | Set by the crystal; quartz-on-Si kept below 570°C throughout |
| Thinning | Grinding + CMP; 50µm-class flow; film target per device physics |
| Surface Finish | CMP below 0.5nm Ra class |
| Flatness | <5µm TTV class on precision carriers |
| Wafer Sizes | 4 inch (100mm), 6 inch (150mm) standard; others per feasibility |
| Metrology | Thickness map, TTV, roughness with every lot; bond inspection |
| Lot Size | 3-5 wafer prototype lots standard; repeat lots on the same recipe |
| Downstream | Lithography, metallization, etching, dicing available on the same line |
Quartz-on-Si for resonators, oscillators, and timing MEMS that want quartz's temperature behavior and Q inside a silicon process flow, the stack our proven inquiry demand is built on.
Thin-film lithium niobate for modulators, frequency conversion, and quantum photonic circuits, prototype substrate lots for the teams inventing on this platform.
Piezo-on-carrier stacks for acoustic-wave device research, filters, sensors, and acoustoelectric experiments, where film thickness is the design variable.
Piezo and electro-optic films on low-loss carriers for microwave-to-optical transduction and hybrid quantum experiments, the substrate half of a very hard problem.
Pressure, force, and inertial sensing concepts that exploit single-crystal films with lithographic patterning, past the limits of deposited polycrystalline layers.
Your crystal-on-carrier idea reviewed before wafers are committed: bond route, thermal budget, thinning plan, and honest risk, then a 3-5 wafer lot to find out.
3-5 wafers is our standard offer in this lane, the exact quantity that gets a device program started and gets refused elsewhere.
Bonding, grinding, CMP, and substrates are established pages of this site; TFOI is their composition, not a new promise.
Quartz's 573°C transition is treated as a hard ceiling with margin, and every stack's budget is engineered the same way.
Crystal sourcing through the substrate program means one RFQ and one accountable flow, not a sourcing project plus a process project.
Thickness maps, TTV, and roughness ship with every lot, so your device model starts from measurements, not hopes.
Lithography, metallization, and dicing continue on the same line, managed end to end by a dedicated project manager.
Share your process requirements, substrate, and production volume. A Nanosystems JP Inc. engineer will respond within 24 hours. Full quote typically within 7-10 business days, subject to project complexity and NDA requirements.