Thin-Film-on-Insulator
Quartz-on-Si, LNOI & Piezo Films
At Nanosystems JP Inc., we build engineered substrates in small prototype lots: crystalline quartz bonded to silicon below 570 °C, keeping the process ceiling under the 573 °C α-β quartz transition, lithium niobate on insulator, and piezoelectric films on Si or sapphire carriers. This flow leverages capabilities already documented on this site: fusion and plasma-activated bonding, grinding and CMP thinning toward 50 µm and below, and the substrate program that sources the crystals. The service is built around what research teams actually need: 3-5 wafer prototype lots, delivered with data, for teams whose device idea starts with a substrate that does not exist yet. Sub-micron device films of the kind used in standard LNOI photonics are treated as engineered-development programs, scoped against target thickness, interface, and loss requirements.
ceiling, below the α-β point
the lot size others refuse
CMP-finished below 0.5 nm Ra
carrier and cap wafers
Volume producers of engineered substrates start at volumes
Established engineered-substrate makers quote in the hundreds of wafers; a research team needs four. That gap is where device programs die, and it is exactly the gap our bonding, grinding and CMP, and substrate programs were built to close, one small, well-documented lot at a time.
Bond, thin, polish:
a substrate built like a device
Every stack on this page is the same three-act play performed with different crystals, and each act is a documented capability.
Act One: The Bond
Fusion and plasma-activated bonding join the functional crystal to its carrier at temperatures the crystal dictates, for quartz-on-Si that means staying below 573°C, the α-β transition, which our low-temperature plasma-activated route respects with margin. Interlayer oxides, and metal or adhesive couples where a stack demands them, come from the same bonding service.
Act Two: The Thinning
The bonded crystal starts as a full-thickness wafer and ends as a film: grinding takes the bulk, CMP takes the damage, and the flow that thins device wafers toward 50 µm carries the same stack thickness control here. Target thickness and uniformity are set per program against your device physics, resonator, waveguide, or transducer.
Act Three: The Finish
CMP finishing below 0.5 nm Ra gives the film a device-ready surface, and metrology closes the loop: thickness maps, TTV, and roughness shipped with each lot as agreed per program, because a prototype substrate without data cannot anchor a device model. Downstream patterning, metallization, and dicing continue in the same project when your program wants the device, not just the wafer.
Bond, thin, finish,
in pictures
The three acts of every TFOI stack, drawn once: full-thickness crystal down to a measured film.
Quartz, lithium niobate,
and the piezo-on-carrier family
Four stack families, all quoted at 3-5 wafer prototype lots, with the crystal sourcing handled through our substrate program so one order covers material and process.
Complete TFOI wafer
parameters
| Parameter | Specification |
|---|---|
| Stack Families | Quartz-on-Si, LNOI, piezo-on-carrier (bonded or deposited AlN / PZT), custom per feasibility |
| Carriers | Si standard; sapphire and others per program via the substrate program |
| Bonding | Fusion, plasma-activated; oxide interlayers; metal / adhesive couples per stack |
| Thermal Budget | Set by the crystal; quartz-on-Si kept below 570°C throughout |
| Thinning | Grinding + CMP; 50 µm-class flow; film target per device physics |
| Surface Finish | CMP below 0.5 nm Ra class |
| Flatness | <5 µm TTV class on precision carriers |
| Wafer Sizes | 4 inch (100 mm), 6 inch (150 mm) standard; others per feasibility |
| Metrology | Thickness map, TTV, roughness with each lot as agreed; bond inspection |
| Lot Size | 3-5 wafer prototype lots standard; repeat lots on the same recipe |
| Downstream | Lithography, metallization, etching, dicing available in the same project |
Where an engineered substrate
is the device idea
Quartz MEMS & Timing
Quartz-on-Si for resonators, oscillators, and timing MEMS that want quartz's temperature behavior and Q inside a silicon process flow, the stack our proven inquiry demand is built on.
LNOI Photonics
Thin-film lithium niobate for modulators, frequency conversion, and quantum photonic circuits, prototype substrate lots for the teams inventing on this platform.
Acoustic & SAW/BAW R&D
Piezo-on-carrier stacks for acoustic-wave device research, filters, sensors, and acoustoelectric experiments, where film thickness is the design variable.
Quantum Transduction
Piezo and electro-optic films on low-loss carriers for microwave-to-optical transduction and hybrid quantum experiments, the substrate half of a very hard problem.
Sensors on Crystal Films
Pressure, force, and inertial sensing concepts that exploit single-crystal films with lithographic patterning, past the limits of deposited polycrystalline layers.
Feasibility Programs
Your crystal-on-carrier idea reviewed before wafers are committed: bond route, thermal budget, thinning plan, and honest risk, then a 3-5 wafer lot to find out.
What makes our TFOI capability
different
Small lots from 3-5 wafers
3-5 wafers is the standard offer for this service, the quantity that gets a device program started.
Composed from documented capability
Bonding, grinding, CMP, and substrates are established pages of this site; TFOI is their composition, not a new promise.
Thermal budgets taken literally
Quartz's 573°C transition is treated as a hard ceiling with margin, and every stack's budget is engineered the same way.
Material and process, one order
Crystal sourcing through the substrate program means one RFQ and one accountable flow, not a sourcing project plus a process project.
Data makes it a substrate
Thickness maps, TTV, and roughness ship with each lot as agreed per program, so your device model starts from measurements, not hopes.
The device can stay here
Lithography, metallization, and dicing continue in the same project, managed end to end by a dedicated project manager.
Start your project.
Initial response typically within one business day.
Share your process requirements, substrate, and production volume. A Nanosystems JP Inc. engineer will give an initial response typically within one business day. Full quote typically within 7-10 business days, subject to project complexity and NDA requirements.