UBM Deposition Services
Ti/Pt/Au · Ti/Ni/Au · Cr/Au · TiW/Au
At Nanosystems JP Inc., we deposit and pattern under-bump metallization: the adhesion, diffusion-barrier, and wettable layers that sit between your bond pad and the solder. Evaporation with lift-off or sputter with etch, as a standalone UBM service under your plated solder, or built into our AuSn and indium bump flows. Wafers ship solder-ready, 4 to 12 inch, from a single wafer.
adhesion · barrier · wettable
Si and compound semis
on stepper lithography
prototype to production
Need the solder bump too?
This UBM is already built into our AuSn and indium bump services. This page is for UBM as its own deliverable: under solder you plate, under wire or stud bumps, or as the finished top metal of your device.
Three jobs, one thin stack:
adhesion, barrier, wettability
Direct soldering to aluminum pads is generally unreliable because of the stable native aluminum oxide, while direct solder contact with copper drives excessive intermetallic growth and metal consumption. UBM supplies the controlled adhesion, diffusion-barrier, and wettable interfaces reliable joining needs.
Adhesion Layer: Ti or Cr
The first tens of nanometers decide whether anything sticks. Titanium or chromium bonds chemically to the pad metal and to the surrounding passivation, anchoring the whole bump against the shear and thermal-cycling loads of flip-chip service. The UBM footprint deliberately overlaps the passivation opening, sealing the pad edge so solder and moisture never reach the pad perimeter.
Diffusion Barrier: Pt, Ni, or TiW
Molten solder consumes unprotected pad metal within a single reflow, forming brittle intermetallics where the joint needs strength most. The barrier layer suppresses interdiffusion and limits consumption of the pad metal through reflow and service. Platinum is the standard under AuSn and indium in photonics and cryogenic work; nickel is the workhorse under SnAg; TiW serves the sputter-etch route. Barrier thickness is chosen for your solder chemistry and the number of reflows the assembly will see.
Wettable Finish: Au
The gold top layer does two things: it protects the barrier from oxidation between our deposition and your bonding, and it dissolves into the solder on contact, giving instant, flux-friendly or fluxless wetting. Because solder wets preferentially on the patterned gold finish, the UBM footprint, together with solder volume and reflow conditions, largely defines the bump diameter and stand-off geometry after reflow. The UBM opening is the bump design.
Evaporation lift-off and sputter etch -
matched to your stack and topography
The same stack can be built two ways, and the right choice depends on the metals in it, the topography under it, and what happens to the wafer next. Our engineers recommend the route; both ship the same inspected, solder-ready result.
Evaporation + Lift-Off
The full stack is deposited by e-beam or thermal evaporation in a single pump-down onto a wafer patterned with a lift-off resist profile, then the resist is dissolved, leaving UBM only in the defined openings. This is quietly the highest-volume use of lift-off in bumping: even when the solder itself is plated elsewhere, the Ti/Pt/Au or Cr/Au underneath is very often evaporated and lifted off.
Lift-off is usually preferred for platinum-bearing stacks, since Pt is hard to etch selectively and cleanly without aggressive chemistry or specialized dry etching. No etch chemistry ever touches the pad, the footprint is set by the resist opening at ±0.5 µm registration, and interfaces stay pristine because all three layers deposit without breaking vacuum.
Sputter + Etch
The stack, classically TiW/Au, is sputtered blanket over the whole wafer, patterned by lithography, and the field metal is etched away. Sputtering gives superior step coverage over passivation edges and topography, and the blanket film doubles as the plating seed when the next step is electroplated solder or Cu, so UBM and seed become one deposition.
| Parameter | Evaporation + Lift-Off | Sputter + Etch |
|---|---|---|
| Pt-bearing stacks | Yes, standard | Lift-off preferred; Pt etch is difficult |
| Step coverage | Line-of-sight | Improved step coverage over edges |
| Edge definition | Resist opening, no undercut | Etch bias, slight undercut |
| Doubles as plating seed | No | Yes, blanket film |
| Best for | Pt stacks, fine pads, pristine interfaces | TiW/Au, plated bumps next, topography |
Four proven stacks,
custom stacks on request
The right stack depends on the solder that lands on it, the pad underneath it, and the thermal history the joint will see. These four cover most of the field; custom stacks are engineered on request.
The opening is the bump:
geometry, barrier, and contact
UBM looks like a finishing step but behaves like a design layer. Three controls decide whether the finished joint performs: footprint geometry, barrier engineering, and the contact underneath it all.
Footprint Defines the Joint
Solder wets the gold and stops at its edge, so the UBM footprint, together with solder volume, opposing-pad geometry, wetting, and reflow conditions, strongly influences the final bump diameter and stand-off height. Openings down to ~5 µm on the lift-off route at ±0.5 µm registration, with overlap onto passivation set per your design rules. We review the bump layout against your solder volume before the run, because a UBM diameter mismatch cannot be fixed downstream.
Barrier Engineered to the Solder
Every solder consumes barrier metal at its own rate, and every additional reflow consumes more. We size the barrier to your solder chemistry and assembly sequence: Pt under AuSn and indium, Ni under SnAg with thickness scaled to reflow count, TiW where the sputter route runs. The stack that survives one reflow and the stack that survives five are different stacks, and we ask about your assembly flow before choosing.
Contact Resistance Starts In-Situ
An aluminum pad grows native oxide in minutes, and UBM deposited over that oxide gives an unreliable, drifting contact. Our pre-clean happens inside the deposition chamber, sputter etch or ion milling immediately before the adhesion layer lands, so the interface never sees air. Contact-resistance coupons processed alongside your wafers verify the result when your device demands it.
Under your solder,
or as your finished top metal
Most bump lines only deposit UBM inside their own bump product. We ship it as its own deliverable, because much of the industry needs exactly that.
Under Plated or Placed Solder
Wafers UBM-finished and ready for your solder: electroplated SnAg or Cu pillar at your line or through the electroplating service, solder-ball placement, paste printing, or preform attach. On the sputter route the blanket TiW/Au doubles as the plating seed: plating resist is patterned on the blanket seed, bumps are plated, the resist is stripped, and the exposed field seed and barrier are etched last. You get a wafer that drops directly into your bumping process.
As the Finished Contact Metal
The same stacks serve as final metallization where no solder follows: Au surfaces for Au-Au thermocompression and cryogenic hybridization, wire-bondable and stud-bump pads, ACF/ACP attach, probe pads, and seal-ring frames for hermetic lids. If your device ends at a clean, bondable gold surface, this is the service that puts it there.
Complete UBM deposition
parameters
| Parameter | Evaporation + Lift-Off | Sputter + Etch |
|---|---|---|
| Wafer Sizes | 4 to 12 inch (100 to 300 mm) | |
| Substrates | Si, CMOS ROIC wafers, InP, GaAs, glass, sapphire; others on request | |
| Pad Metals | Al, Cu, Au pads; RDL top metal | |
| Standard Stacks | Ti/Pt/Au, Ti/Ni/Au, Cr/Au | TiW/Au |
| Custom Stacks | Ti/Cu, NiV, Pd finishes, and others on request | |
| Deposition | E-beam and thermal evaporation | Sputter |
| Total Stack Thickness | 0.2 to 1 µm typical, thicker on request | |
| Thickness Control | Quartz crystal monitor | |
| Minimum UBM Opening | ~5 µm typical, finer on request | ~10 µm typical |
| Alignment Accuracy | ±0.5 µm (stepper) | ±1 µm |
| Pre-Clean | In-situ sputter etch / ion milling before deposition | |
| Patterning | Lift-off | Litho + wet / dry etch |
| Plating Seed Function | No | Yes, blanket film as seed |
| Compatible Solders | AuSn, In, SnAg, cryogenic In alloys; wire bond and Au-Au TC finishes | |
| Inspection | Adhesion tape test standard; stud pull, shear, contact-R coupons on request | |
| Electroless Alternative | ENIG / ENEPIG via the electroplating service | |
| Minimum Lot | From 1 wafer; R&D runs to repeat lots on one baseline recipe | |
UBM across photonics, cryo,
and advanced packaging
Photonics Laser & PIC Attach
Ti/Pt/Au under AuSn is the standard metallurgy for laser diode attach, PIC flip-chip, and hermetic photonic packages. The Pt barrier stays effective under eutectic AuSn through reflow and service life, protecting the pad while the Au surface delivers fluxless wetting on optical assemblies.
Cryogenic & Quantum Hybridization
UBM on ROIC and detector wafers under indium bumps, and Au finishes for cold-weld and thermocompression hybridization. Deposited within the strict thermal budgets that CMOS readout and qubit circuits demand, with pad registration matched to fine-pitch FPA arrays.
Compound Semiconductor Devices
Contact and attach metallization on GaAs, InP, GaN, and SiC: MMIC bond pads, die-attach preparation for eutectic metallurgies, and probe pads. Evaporation lift-off is the native patterning route on III-V wafers, where wet etch selectivity is a constant problem.
Flip-Chip on Al and Cu Pads
Ti/Ni/Au over aluminum or copper pads makes standard CMOS wafers solderable for SnAg flip-chip and C4-style assembly. Barrier thickness scaled to the reflow count of your assembly sequence, with the passivation overlap sealing the pad edge for reliability.
WLP and RDL Top Finish
UBM as the final layer over redistribution: the solderable termination of fan-in and fan-out wafer-level packages, and the landing metal for ball drop or plated bumps over RDL copper. Runs as the natural last step after our RDL fabrication flow.
Wire Bond, Stud & ACF Pads
Bondable Au surfaces where no solder is involved: wire-bond pads on devices whose top metal is not bondable, Au stud bump bases, and pad finishes for anisotropic conductive film and paste attach in display and sensor modules.
Hermetic Seal Rings
Patterned Ti/Pt/Au frames around device perimeters, the solderable base for AuSn and indium seal rings in hermetic MEMS, photonic, and cryogenic packages. Frame and pad UBM deposit in the same run, keeping seal and interconnect metallurgy identical.
R&D and Mixed-Die Runs
Single-wafer UBM runs for university and corporate R&D: new device concepts that need a bondable surface, mixed die on one wafer, and process development lots. The same recipe carries the project from single-wafer R&D runs through repeat fabrication on an established baseline process.
What makes our UBM capability
different
Standalone UBM as a real product
Most bump lines only deposit UBM inside their own bump product. We ship UBM-only wafers, under solder you plate, under balls you place, or as your finished contact metal, inspected and documented as a deliverable in its own right.
Both routes, one recommendation
Evaporation lift-off and sputter etch are both available, so the stack is chosen for your solder and topography, not for whichever tool a line happens to run. Pt stacks go lift-off, seed-plus-UBM jobs go sputter, and we tell you why.
In-situ pre-clean, every run
The pad oxide is removed by sputter etch or ion milling inside the chamber immediately before deposition, so the adhesion interface never sees air. That is the difference between a contact resistance you measure once and one you fight forever.
Barrier engineered to your assembly
We ask what solder lands on the stack, how many reflows follow, and what the service temperature is, then size the barrier to that history. The stack is designed to your assembly flow, not copied from a datasheet.
Connected to the full flow
Lithography, deposition, plating, and the AuSn and indium bump services run as one process flow, managed end to end by a dedicated project manager. UBM can be a standalone deliverable or step one of your complete bumping program.
From 1 wafer, no minimum lot
Prototype UBM on a single wafer, verify adhesion, thickness, and contact resistance before committing to volume. The prototype data becomes the baseline for repeat production on the same recipe.
Pillars with SnAg caps and SnAg bumps on your pad stack and pitch.
Check a thermal budget
Enter your device's maximum temperature to see which processes fit. Typical windows: evaporation and sputtering with lift-off 20 to 150 °C; PVD AuSn and solder metals to 150 °C; ALD 80 to 300 °C; PECVD 150 to 400 °C; AuSn eutectic ~280 °C; AuSi ~363 °C; Al-Ge ~424 °C; anodic bonding 300 to 450 °C; thermal oxidation 900 to 1100 °C; SiC implant activation 1400 to 1800 °C. Confirmed per program.
Start your project.
Initial response typically within one business day.
Share your process requirements, substrate, and production volume. A Nanosystems JP Inc. engineer will give an initial response typically within one business day. Full quote typically within 7-10 business days, subject to project complexity and NDA requirements.