How we work

How to Order
and Prepare an RFQ

Everything a first inquiry needs: what to send, how a quotation is built, when lead time starts, and how universities and research groups can buy from us. Your information stays confidential; an NDA is available whenever you want one. Prototype orders from one wafer; chips and coupons by review.

Ready now? Open the Technical RFQ form →

GDS · DXF · DWG · PDFNDA available on requestQuote in 7-10 business daysFrom 1 waferUniversities welcome
1 day
Initial engineering
response target
7-10
Business days to quote
after information is complete
1
Wafer minimum
order
4-8 wk
Typical lead time
single flow
Step 1

What to send with a first inquiry

Including the information below helps us assess feasibility and identify any follow-up questions. Additional technical review may be needed for complex or custom processes.

01

Substrate and size

Material (Si, SiC, GaN, GaAs, InP, glass, sapphire, ceramic), diameter or panel size, thickness, orientation, and surface finish. Say whether you supply the substrates or we do.

02

Process and stack

The processes you need in order (for example lithography, etch, deposition, bonding, bumping), the film stack with target thicknesses, and any process you have already done on the wafers, including existing metal.

03

Design data

GDSII, DXF, or DWG is best; PDF drawings and dimensioned sketches are welcome for an initial review; any CAD conversion or mask-data preparation is scoped and quoted separately where required. Mark the critical dimensions, tolerances, and which layer is which.

04

Target versus acceptance

Tell us what you are aiming for (target properties) separately from what you will accept or reject a lot on (acceptance specifications). Feasibility, acceptance criteria, inspection methods, and sampling are agreed in writing before fabrication.

05

Quantity and stage

Number of wafers, chips, coupons, or panels, and whether this is a feasibility trial, prototype, pilot, or repeat lot. From 1 wafer is fine.

06

Schedule and constraints

Target date, thermal budget of finished devices, export-control status of the design, and any material or chemistry the wafers must not see.

Step 2

Confidentiality, and the NDA when you want one

We treat the project information you share as confidential and use it to evaluate your inquiry and, if you proceed, to perform the agreed project work. For a first feasibility answer the outline is enough: substrate, process list, dimensions, quantity, and budget range. That usually lets us give you an initial view on fit and a budget indication quickly, before anyone spends time on paperwork.

07

Share the outline first

A short description without proprietary detail is the fastest route to an initial feasibility view and a budget indication. Most programs start this way.

08

NDA at any stage

You can request a mutual NDA at any stage; we arrange execution once both parties agree on the terms. It can come before the first call or after the budget is confirmed, whichever suits you.

09

Export-controlled data

Tell us before sending technical data that is subject to export control; we confirm in writing that we can receive it and that any required authorizations are in place.

10

File transfer

Share design files by a link to your own drive (Google Drive, OneDrive, Box, or your transfer server) or by encrypted attachment. We confirm receipt and the file list before review.

Step 3

How a quotation is built

We aim to provide an initial engineering response within one business day. Feasibility review and quotation timing depend on the project and the information available; written quotations are typically prepared within 7-10 business days after the required information is complete.

01Inquiry02Initial response03Process definition04Written quotation05Order06Confirmation07Fabrication08ShippingTargets: initial response within one business day; written quotation typically 7-10 business days after the information is complete
StageWhat happensWhat you receive
Initial response (target: one business day)A process engineer acknowledges the inquiry, checks the outline against the requested substrate, geometry, and stack, and lists open questions.Initial view on fit and, if needed, a short list of questions
Process definitionWe prepare a proposed process flow and inspection plan, including any required masks or tooling, for your confirmation.Draft flow for your confirmation
Written quotation (7-10 business days)Price per lot and per wafer, NRE if any, masks and tooling, inspection deliverables, lead time and its start conditions, validity period, payment terms.Formal quotation (PDF), English or Japanese
OrderSubmit a purchase order or signed quotation. Payment terms and any required advance payment are specified in our quotation.Order confirmation
Pre-fabrication confirmationFor programs with masks or new stacks: final layer thicknesses, mask layouts, and acceptance criteria signed off before fabrication is released.Confirmation document to sign
Fabrication and inspectionRuns under the traveler; inspection at the agreed points (optical, dimensional, CD-SEM, electrical, or others as agreed).Status updates at milestones, inspection data as agreed
ShippingWafers in cassettes or single-wafer carriers, masks in shipping boxes, N₂ purge where specified; tracked worldwide delivery with export paperwork.Shipment notice and tracking
Step 4

Development costs, inspection, and lead time

11

NRE and development

Standard processes are quoted per lot. Non-standard stacks, new materials, or geometry outside qualified ranges carry a development charge (design review, test coupons, characterization) quoted as a separate line so you can see what is one-time and what repeats.

12

Inspection included

Inspection is defined per project. Typical deliverables are optical inspection and dimensional data; CD-SEM, cross-section SEM, sheet resistance, film thickness, and electrical test are available by agreement and listed in the quotation.

13

When lead time starts

Lead time starts when the conditions specified in the quotation are met: normally confirmed design data, substrates on hand (yours or ours), the order, and any advance payment stated in the quotation. Typical lead time is 4-8 weeks for a single-process flow. Lead time for multi-process and development projects is confirmed in the quotation and may be longer. Lead time begins when the start conditions specified in the quotation are fulfilled.

14

Customer-supplied substrates

Welcome. Send the material, diameter, thickness, orientation, finish, and process history; wafers carrying existing metal are reviewed before acceptance. We record incoming condition before the first step.

15

Changes after order

Specification changes are handled through a written change note with any cost or schedule effect stated before we proceed.

16

Repeat lots

A completed prototype flow is kept on file for repeat lots. For repeat orders, confirm the process revision, substrate condition, quantity, and required date, and tell us about any changes since the previous lot.

Universities and research institutes

Procurement for research groups

We welcome inquiries from universities and public research institutes. The process is the same; the paperwork is adapted to yours.

17

Quotations and invoices

Formal quotations and invoices in English or Japanese, in JPY or USD, addressed to the institution and referencing your grant or project number where required.

18

Purchase orders

Tell us your institution's purchase-order, supplier-registration, and invoicing requirements before quotation. We will confirm the documentation and payment terms we can support.

19

Small lots

From 1 wafer, coupons, or diced pieces; no minimum lot, so a thesis project can buy exactly what it needs.

20

Student and lab communication

Engineers correspond in English or Japanese directly with the researcher; we can join a short video call to define the flow before quoting.

Before you send

One-minute checklist

  • Substrate material, size, thickness, and who supplies it
  • Process list in order, with film stack and thicknesses
  • Design file (GDS/DXF/DWG) or a dimensioned drawing, with critical dimensions and tolerances
  • Quantity and unit (wafers, chips, coupons, panels) and program stage
  • Target date and any thermal, chemical, or export constraints
  • Whether you would like an NDA (available at any stage)

Start your project.
Response within 24 hours.

Share your process requirements, substrate, and production volume. A Nanosystems JP Inc. engineer will respond within 24 hours. Full quote typically within 7-10 business days, subject to project complexity and NDA requirements.

To speed up technical review, please include:
substrate type & size  ·  target process  ·  quantity  ·  timeline  ·  design files if available (not required for first review)

[email protected] · +81-3-5288-5569 · NDA available · All inquiries handled confidentially

Ready to discuss this process?
Technical review within 24 hours of inquiry. NDA available.
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All Services
Full process flow →
Substrates
Substrate & WafersSi, SiC, GaN, glass, sapphire Fused Silica WafersQuartz · borosilicate · low CTE PI Film & SUS Sensor FabRoll-to-roll · sensor patterning
Front-End
Mask FabricationGDS to chrome mask, DRC PhotolithographyE-beam 20nm to 500×600mm NanoimprintingUV & thermal NIL Thin Film DepositionPVD, CVD, ALD, MBE LiftoffMetal pattern · shadow mask ElectroplatingCu TSV fill, DPC, LIGA EtchingICP-RIE, DRIE >50:1 AnnealingN₂/H₂/vacuum/RTA Ion ImplantationB/P/As/Al/N implant CMP & GrindingCu CMP, 50µm thinning DicingBlade, stealth laser Wafer CleaningRCA, plasma, megasonic
Advanced Packaging
Wafer BondingHybrid, eutectic, fusion TSV FabricationHigh AR, void-free Cu fill TSV RevealBackgrind → etch → CMP TGV FabricationThrough-glass via RDL FabricationBCB/PBO/PI + damascene Packaging & AssemblyWire bond, flip-chip 📚 3D/2.5D PackagingTSV+RDL+UBM+C4 AuSn BumpPVD lift-off, fluxless Indium BumpEvap lift-off · cryo/quantum UBM DepositionTi/Pt/Au · adhesion-barrier-Au Gold BumpEvap & plated · Au-Au TC AuGe / AuSi356/363°C eutectic die attach High-Pb Bumps95Pb5Sn · hi-rel C4 SLID / TLPCu/Sn · Au/In · Ag/In Al-Ge Sealing424°C · CMOS-friendly MEMS Ohmic ContactsGaAs · GaN · RTA + TLM Cryo & UHV MetallizationAuSn · Ti/Pd/Au · seal rings Optical AccessWindows · meshes · thru-holes MEMS Vapor CellsDRIE + bond · unfilled bodies Thin-Film-on-InsulatorQuartz-on-Si · LNOI Biochip & MicrofluidicsGlass 500×600mm, NIL SiPho PackagingTSV·RDL·UBM·C4 for PIC
Industries
AI & HPC PackagingCoWoS-style, 2.5D/3D Silicon PhotonicsSOI · AuSn · TSV interposer Quantum TechnologyIon traps · vapor cells · TFOI AutomotiveMEMS sensors, SiC power Life SciencesLab-on-chip, biosensors All Industries → Request a Quote →
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Capabilities Overview
Substrates
Substrate & WafersSi, SiC, GaN, glass, sapphire Fused Silica WafersQuartz · borosilicate · low CTE PI Film & SUS Sensor FabRoll-to-roll · sensor patterning
Front-End
Mask FabricationGDS to chrome mask, DRC PhotolithographyE-beam 20 nm to 500×600 mm NanoimprintingUV & thermal NIL Thin Film DepositionPVD, CVD, ALD, MBE TFT & BackplaneIGZO · Glass · Display LiftoffMetal pattern · shadow mask ElectroplatingCu TSV fill, DPC, LIGA EtchingICP-RIE, DRIE >50:1 AnnealingN₂ / H₂ / vacuum / RTA Ion ImplantationB / P / As / Al / N implant CMP & GrindingCu CMP, 50 µm thinning DicingBlade, stealth laser Wafer CleaningRCA, plasma, megasonic
Advanced Packaging
Wafer BondingHybrid, eutectic, fusion TSV FabricationHigh AR, void-free Cu fill TSV RevealBackgrind → etch → CMP TGV FabricationThrough-glass via RDL FabricationBCB / PBO / PI + damascene Packaging & AssemblyWire bond, flip-chip 3D / 2.5D PackagingTSV + RDL + UBM + C4 AuSn BumpPVD lift-off, fluxless Indium BumpEvap lift-off · cryo/quantum UBM DepositionTi/Pt/Au · adhesion-barrier-Au Gold BumpEvap & plated · Au-Au TC AuGe / AuSi356/363°C eutectic die attach High-Pb Bumps95Pb5Sn · hi-rel C4 SLID / TLPCu/Sn · Au/In · Ag/In Al-Ge Sealing424°C · CMOS-friendly MEMS Ohmic ContactsGaAs · GaN · RTA + TLM Cryo / UHV MetalAuSn · Ti/Pd/Au · rings Optical AccessWindows · meshes · holes Vapor CellsDRIE + bond · unfilled TFOI WafersQuartz-on-Si · LNOI Biochip & MicrofluidicsGlass 500×600 mm, NIL SiPho PackagingTSV · RDL · UBM · C4 for PIC
Industries
AI & HPC PackagingCoWoS-style, 2.5D / 3D Silicon PhotonicsSOI · AuSn · TSV interposer AutomotiveMEMS sensors, SiC power Life SciencesLab-on-chip, biosensors All Industries → Request a Quote →