Ohmic Contact Metallization
GaAs · GaN · InP Systems, RTA Alloyed
At Nanosystems JP Inc., we deposit and pattern the ohmic contact systems of compound semiconductor manufacturing: AuGe/Ni/Au on n-GaAs, Ti/Al/Ni/Au on GaN and AlGaN, Ni/Au and related stacks across the III-V family. Evaporated in one pump-down with in-situ pre-clean, lift-off patterned at ±0.5 µm, alloyed by rapid thermal annealing to your recipe, and verified with TLM test structures on request. These are lift-off processes, like the bump metals, and on a compound semiconductor program they are scheduled within the same project. 4 to 12 inch, from a single wafer.
GaAs, GaN, general III-V
interfaces stay protected
on stepper lithography
coupons on request
Contacts and bumps share the evaporators
Ohmic stacks are not bumps, but they are lift-off processes like the bump metals, and on a compound semiconductor program they are scheduled together. AuGe die attach lives on the AuGe / AuSi page; front-side contacts, alloying, and TLM verification live here. One program can carry both.
Contact resistance is made
at deposition and anneal
An ohmic contact is a recipe with three failure points: the interface before deposition, the stack itself, and the alloying step. We control all three in one flow.
The Standard Systems, Deposited Right
Decades of III-V manufacturing settled the metallurgies: AuGe/Ni/Au for n-GaAs, Ti/Al-based stacks for GaN, Ni/Au and platinum-group variants elsewhere. What separates a good contact from a drifting one is execution: an in-situ sputter or ion-mill pre-clean immediately before deposition to reduce interface oxide, then the full stack in one pump-down with vacuum breaks between layers minimized.
RTA Alloying to Your Recipe
Most ohmic systems only become ohmic after alloying, the rapid thermal anneal that drives the contact reaction into the semiconductor. Our RTA runs in the same flow as deposition, executed to your time-temperature recipe and ambient, so the wafer that leaves is a finished, alloyed contact, not a kit of parts. High-temperature GaN recipes are confirmed against the program at RFQ.
Verified, Not Assumed
Contact resistance is a measured quantity, and the transfer length method is how the field measures it. TLM test structures patterned alongside your devices, processed through the identical deposition and anneal, give specific contact resistivity data on request, the number your device model actually needs, from your actual wafer.
GaAs, GaN, and the wider
III-V contact menu
All systems deposit by evaporation with in-situ pre-clean and pattern by lift-off, the standard route on compound semiconductors, where wet-etch selectivity is a permanent headache.
Complete ohmic contact
parameters
| Parameter | Specification |
|---|---|
| Standard Systems | AuGe/Ni/Au (n-GaAs), Ti/Al/Ni/Au (GaN/AlGaN), Ni/Au (p-GaN, III-V) |
| Custom Systems | Pd-, Pt-, Ge-based and others, per your published recipe |
| Wafer Sizes | 4 to 12 inch (100 to 300 mm) |
| Substrates | GaAs, GaN on Si / SiC / sapphire, InP; others on request |
| Deposition | E-beam / thermal evaporation, one pump-down, in-situ pre-clean |
| Patterning | Lift-off, ±0.5 µm registration |
| Typical Stack Thickness | 0.1 to 0.5 µm, per system and recipe |
| Alloying | RTA in flow, time-temperature-ambient per recipe; high-temp GaN confirmed per program |
| Verification | TLM structures and specific contact resistivity on request; profilometry + SEM standard |
| Minimum Lot | From 1 wafer; R&D runs to repeat lots on one baseline recipe |
Contacts across the compound
semiconductor field
GaAs MESFET, HEMT & MMIC
AuGe/Ni/Au source-drain and pad contacts for the GaAs RF front-end world, alloyed to recipe, with TLM data available for the device models telecom and radar programs run on.
GaN Power & RF HEMTs
Ti/Al/Ni/Au ohmics for GaN-on-Si and GaN-on-SiC HEMTs in power conversion and RF amplification, the contact that sets on-resistance before the channel gets a say.
LEDs & Laser Diodes
n- and p-side contact metallization for GaN and III-V emitters, from research epi to production structures, annealed to the balance of contact resistance and optical constraint your device demands.
InP Photonics & HBTs
Contact systems for InP photonic devices and HBT structures, deposited on the substrates our photonics customers already run through the bump and die-attach flows.
University & Research Epi
Contacts on novel epi and device concepts from a single wafer, with TLM structures included so the first publication carries measured contact resistivity, not an assumption.
Full Front-to-Back Programs
Front-side ohmics, backside die-attach metallization, and bumps in one coordinated program, delivered as a service.
What makes our contact capability
different
The interface is protected
In-situ pre-clean immediately before deposition, then the whole stack in one vacuum. The contact interface never sees air, which is where drifting contacts are born.
Deposition and anneal, one flow
The alloying step ships with the deposition, executed to your recipe, so you receive finished ohmic contacts rather than metal awaiting a furnace.
Numbers, not adjectives
TLM coupons through the identical process give specific contact resistivity on request. "Low resistance" is a measurement here, not a brochure word.
Lift-off on III-V, natively
Compound semiconductors punish wet etching and reward lift-off, and lift-off is the discipline this entire line is built on.
One module, whole program
Ohmics, backside metal, die attach, and bumps share the evaporators and run as one program, managed end to end by a dedicated project manager.
From 1 wafer, no minimum lot
Prototype contacts on a single wafer, measure the TLM, then scale on the same recipe with the data as baseline. That prototype data becomes the baseline for repeat production.
Dedicated pages that start from this process
Contacts, implantation, 1800 °C activation, cleaning and thinning on 4H-SiC as one program.
Contacts, mesa etch, passivation and vias on GaN, GaAs and InP.
Start your project.
Initial response typically within one business day.
Share your process requirements, substrate, and production volume. A Nanosystems JP Inc. engineer will give an initial response typically within one business day. Full quote typically within 7-10 business days, subject to project complexity and NDA requirements.