Thermal development

Silicon Microchannel
Cooling Structures

Etched silicon channels, bonded flow structures, and heater or sensor test chips, built from your drawing and your operating conditions. Choose the stage: open etched parts, a bonded cold plate, or a thermal test vehicle with inspection agreed before the run.

Deep etching capability →

Etched channelsBonded coversPorts and manifoldsHeater test chipsLeak and pressure testsFrom 1 wafer
Your drawing
Channel, manifold,
and port geometry
Open or bonded
Delivered at the
stage you need
Si + glass
Cover materials
reviewed per design
1
Wafer minimum
for a first lot
Fabrication options

Turn a cooling concept into physical parts

Choose the stage you need, from an etched silicon coupon to a bonded structure or thermal test vehicle. Each project starts with a review of geometry, materials, and operating conditions.

channels etched in Siports and bond landscover bondedheater test chipSchematic cross sections; dimensions are designed per program.
01

Etched silicon structures

Patterned channels with a defined remaining silicon thickness; inlet, outlet, and mounting features reviewed with the design; open structures for inspection, assembly trials, or further processing.

02

Bonded flow structures

Lid material, ports, and bond lands considered together; bonding temperature and fluid compatibility reviewed before the route is fixed; seal inspection or fluidic tests included when agreed.

03

Heater and sensor test chips

Custom heater pattern with its electrical contact layout; NiCr or another suitable heater film reviewed per design; temperature-sensor structures where the layout provides access.

Define the thermal stack

The channel is one part of the cooling assembly

A silicon cold plate is evaluated against a heater or a test die through a specified thermal interface. Fluidic connections, cover material, bond lands, and the mounting arrangement are reviewed together.

Channel geometry

Channel width, depth, wall thickness, and base thickness, with the manifold layout that feeds them.

Ports and sealing

Inlet and outlet access, seal layout, and the connection method your fixture uses.

Heat source and interface

Heat-source footprint, thermal interface material, and mounting load.

Operating conditions

Coolant, flow conditions, pressure, and the intended test temperature.

Design and feasibility

Tell us what the structure has to do

Send a drawing and the intended operating conditions. They define the fabrication scope, the interfaces, and the dimensional and inspection requirements.

ParameterWhat to include in your inquiry
Substrate and formatSilicon wafer or coupon dimensions, thickness, orientation if specified, and surface condition.
Channel geometryWidth, depth, spacing, minimum wall thickness, channel length, manifold layout, and the remaining base thickness.
Ports and connectionsInlet and outlet positions, opening dimensions, through-hole requirements, and the external connection method.
Cover and bondingOpen or covered structure; lid material and thickness, bond-land layout, and the acceptable bonding temperature.
Fluidic conditionsIntended coolant, flow range, operating pressure and temperature, and any leak-test requirement.
Thermal test vehicleHeat-source dimensions, heater pattern, target resistance or applied power, and sensor locations.
Delivery and acceptanceQuantity, target date, wafer or diced-part format, required dimensional data, and the agreed acceptance criteria.
Coordinated fabrication

A defined route from drawing to test part

The flow depends on whether you need open channels, a bonded structure, or a heater and sensor test chip.

  1. Drawing and interface review. Channel geometry, ports, bond lands, remaining thickness, handling, and the intended thermal interface.
  2. Mask and patterning. Prepare the layout and pattern the masking layers for channels, manifolds, ports, or thin-film structures.
  3. Silicon etching. Etch the approved channel and cavity features; dimensions and remaining material checked against the agreed process window.
  4. Ports and surface preparation. Complete the selected openings and prepare surfaces for the next step, including any cleaning or metal layers.
  5. Cover bonding, when specified. Join the channel structure to the chosen lid by the approved bond route, with agreed inspection.
  6. Inspection and delivery. Wafers or diced parts with the agreed geometry data and any electrical or fluidic results.
Inspection and delivery

Measure the features that matter to your test

Define the inspection plan before fabrication. Functional evaluation needs the fixture, coolant, connections, and operating conditions specified.

01

Channel and port geometry

Optical inspection and dimensional measurement of channel width, depth, port openings, and remaining thickness.

02

Bonded interfaces

Inspection of the bonded structure by a method suited to the lid, bond material, and geometry.

03

Fluidic evaluation

Leak or pressure tests scoped with the test fluid, fixture, pressure, duration, and acceptance criteria.

04

Electrical test structures

Heater resistance, continuity, and temperature-sensor calibration where the test-chip design provides access.

Delivery: open etched silicon wafers or diced channel coupons, bonded flow structures with the agreed inspection record, patterned heater or temperature-sensor test chips, with optional metallization, dicing, and characterization.

Applications

For the next stage of thermal development

AI and HPC cooling research

Local heat removal, package interfaces, and microfluidic cooling concepts on real silicon rather than in simulation only.

Power and RF thermal development

Cold plates and test vehicles for devices where heat flux is concentrated in a small area.

Materials and equipment evaluation

Repeatable structures for coolant, interface material, and bonding evaluations.

Project questions

Before you send a cooling design

Can you fabricate our own channel and manifold pattern?

Yes. Send the channel width and depth, wall and base thicknesses, port geometry, substrate dimensions, and a drawing or layout file; the supported geometry is confirmed at review.

Does the service include a complete cooling system?

The scope covers etched parts, specified bonding, test structures, and agreed inspection. Pumps, external manifolds, connectors, control electronics, and system-level qualification are outside it.

Can you etch channels into completed electronic devices?

Processing active devices needs a separate feasibility review: incoming layer stack, protection strategy, remaining silicon thickness, contamination restrictions, and thermal budget all matter.

Can you provide a heater chip for evaluating our cold plate?

A patterned resistive heater with a temperature-sensor layout can be quoted as a separate test vehicle. Specify heated area, power distribution, target resistance, and operating temperature.

What is needed for leak and thermal testing?

For fluidic tests: coolant, connections, fixture, flow, pressure, temperature, and acceptance criteria. For thermal tests, also the heat-source distribution and thermal interface.

Start your project.
Response within one business day.

Share your process requirements, substrate, and production volume. A Nanosystems JP Inc. engineer will respond within one business day. Full quote typically within 7-10 business days, subject to project complexity and NDA requirements.

To help us review your design, please include:
substrate type & size  ·  target process  ·  quantity  ·  timeline  ·  design files if available (not required for first review)

[email protected] · +81-3-5288-5569 · NDA available · All inquiries handled confidentially

Ready to discuss this process?
Technical review within one business day of inquiry. NDA available.
Request a Quote →
All Services
Full process flow →
Substrates
Substrate & WafersSi, SiC, GaN, glass, sapphire Fused Silica WafersQuartz · borosilicate · low CTE PI Film & SUS Sensor FabRoll-to-roll · sensor patterning
Front-End
Mask FabricationGDS to chrome mask, DRC PhotolithographyE-beam 20nm to 500×600mm NanoimprintingUV & thermal NIL Thin Film DepositionPVD, CVD, ALD, MBE LiftoffMetal pattern · shadow mask ElectroplatingCu TSV fill, DPC, LIGA EtchingICP-RIE, DRIE >50:1 AnnealingN₂/H₂/vacuum/RTA Ion ImplantationB/P/As/Al/N implant CMP & GrindingCu CMP, 50µm thinning DicingBlade, stealth laser Wafer CleaningRCA, plasma, megasonic
Advanced Packaging
Wafer BondingHybrid, eutectic, fusion TSV FabricationHigh AR, void-free Cu fill TSV RevealBackgrind → etch → CMP TGV FabricationThrough-glass via RDL FabricationBCB/PBO/PI + damascene Packaging & AssemblyWire bond, flip-chip 📚 3D/2.5D PackagingTSV+RDL+UBM+C4 AuSn BumpPVD lift-off, fluxless Indium BumpEvap lift-off · cryo/quantum UBM DepositionTi/Pt/Au · adhesion-barrier-Au Gold BumpEvap & plated · Au-Au TC AuGe / AuSi356/363°C eutectic die attach High-Pb Bumps95Pb5Sn · hi-rel C4 SLID / TLPCu/Sn · Au/In · Ag/In Al-Ge Sealing424°C · CMOS-friendly MEMS Ohmic ContactsGaAs · GaN · RTA + TLM Cryo & UHV MetallizationAuSn · Ti/Pd/Au · seal rings Optical AccessWindows · meshes · thru-holes MEMS Vapor CellsDRIE + bond · unfilled bodies Thin-Film-on-InsulatorQuartz-on-Si · LNOI Biochip & MicrofluidicsGlass 500×600mm, NIL SiPho PackagingTSV·RDL·UBM·C4 for PIC
Industries
AI & HPC PackagingCoWoS-style, 2.5D/3D Silicon PhotonicsSOI · AuSn · TSV interposer Quantum TechnologyIon traps · vapor cells · TFOI AutomotiveMEMS sensors, SiC power Life SciencesLab-on-chip, biosensors All Industries → Request a Quote →
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Capabilities Overview
Substrates
Substrate & WafersSi, SiC, GaN, glass, sapphire Fused Silica WafersQuartz · borosilicate · low CTE PI Film & SUS Sensor FabRoll-to-roll · sensor patterning
Front-End
Mask FabricationGDS to chrome mask, DRC PhotolithographyE-beam 20 nm to 500×600 mm NanoimprintingUV & thermal NIL Thin Film DepositionPVD, CVD, ALD, MBE TFT & BackplaneIGZO · Glass · Display LiftoffMetal pattern · shadow mask ElectroplatingCu TSV fill, DPC, LIGA EtchingICP-RIE, DRIE >50:1 Microchannel CoolingEtched, bonded, heater test chips AnnealingN₂ / H₂ / vacuum / RTA Ion ImplantationB / P / As / Al / N implant CMP & GrindingCu CMP, 50 µm thinning Patterned Test WafersCustom CMP and process evaluation wafers DicingBlade, stealth laser Wafer CleaningRCA, plasma, megasonic
Advanced Packaging
Wafer BondingHybrid, eutectic, fusion TSV FabricationHigh AR, void-free Cu fill TSV RevealBackgrind → etch → CMP TGV FabricationThrough-glass via Glass TGV CouponsHole-only to routed prototypes RDL FabricationBCB / PBO / PI + damascene Packaging & AssemblyWire bond, flip-chip 3D / 2.5D PackagingTSV + RDL + UBM + C4 AuSn BumpPVD lift-off, fluxless Laser SubmountsSi/AlN submounts, optical benches Indium BumpEvap lift-off · cryo/quantum UBM DepositionTi/Pt/Au · adhesion-barrier-Au Cu Pillar & SnAg BumpingPillars with SnAg caps, SnAg bumps Gold BumpEvap & plated · Au-Au TC AuGe / AuSi356/363°C eutectic die attach High-Pb Bumps95Pb5Sn · hi-rel C4 SLID / TLPCu/Sn · Au/In · Ag/In Al-Ge Sealing424°C · CMOS-friendly MEMS Ohmic ContactsGaAs · GaN · RTA + TLM Cryo / UHV MetalAuSn · Ti/Pd/Au · rings Optical AccessWindows · meshes · holes Vapor CellsDRIE + bond · unfilled TFOI WafersQuartz-on-Si · LNOI Biochip & MicrofluidicsGlass 500×600 mm, NIL SiPho PackagingTSV · RDL · UBM · C4 for PIC
Industries
AI & HPC PackagingCoWoS-style, 2.5D / 3D Silicon PhotonicsSOI · AuSn · TSV interposer AutomotiveMEMS sensors, SiC power Life SciencesLab-on-chip, biosensors All Industries → Request a Quote →