Process development

Glass Interposer Prototyping
and TGV Test Coupons

Glass test vehicles built to the stage your work starts from: hole-only coupons, seeded or lined vias, filled vias, and routed interposer prototypes. Customer-supplied pre-drilled glass can be reviewed and metallized.

Production TGV interposers →

Hole-only couponsSeed and liningFilled viasRouted prototypesCustomer glass reviewedWafer or panel format
20 µm
Minimum via diameter
larger on request
10:1
Filled via
aspect ratio
20:1
Hollow via
typical
4 stages
Hole, seed, lined,
or filled delivery
What you can order

Start with the part of the flow you need

Use a coupon to isolate one process question, or combine agreed steps into an interposer prototype. Each delivery state is a distinct order.

01

Hole-only TGV coupons

Via diameter, pitch, profile, and substrate thickness reviewed together; arrays, isolated vias, and defined inspection fields; handling, edge quality, and cleanliness requirements scoped for your next process.

02

Metallized via coupons

Seeded, sidewall-lined (open centre), or filled vias, with the plating contact, adhesion route, and inspection access considered from the start.

03

Routed glass prototypes

Front- and back-face routing on the metallized glass, with dielectric and pad finish defined; customer pre-drilled glass reviewed for incoming condition.

hole onlyseededlined (open centre)filledSchematic cross sections: glass (grey), seed (light copper), Cu (copper).
Design and feasibility

Glass, geometry, and metal work together

Share both the starting substrate and the finished cross-section. Process compatibility is reviewed across the whole sequence, not step by step.

ParameterWhat to include in your inquiry
Glass and formatManufacturer and grade where known, composition or material data, wafer or coupon size, thickness, and total thickness variation if specified.
Via geometryEntry, exit, and minimum internal diameter; substrate thickness, via pitch, array size, and shape (through, blind, tapered, hourglass).
Incoming conditionUnprocessed or pre-drilled glass, existing films, hole condition, cleaning history, and any surface treatment already applied.
Metallization endpointSeed-only, sidewall-lined, or filled; preferred adhesion and barrier layers, Cu thickness, and the finish required by your next step.
Routing and interfacesFront- and back-face layouts, coordinate orientation, dielectric stack, line and space, pad finish, and alignment requirements.
Inspection and deliveryQuantity, destructive sampling allowance, dimensional and electrical criteria, and wafer or diced coupon format.
Coordinated fabrication

One defined route from glass to coupon

The sequence below includes optional stages. Your quotation names the starting material, the steps included, and the final delivery condition.

  1. Review the test vehicle. Agree the glass grade, via geometry, layout orientation, endpoint, and measurement plan.
  2. Form or receive vias. Produce the hole pattern, or inspect customer-supplied pre-drilled glass for profile, cleanliness, and handling condition.
  3. Prepare and seed. Apply the agreed surface preparation and adhesion or seed route, with coverage through the via considered.
  4. Build the Cu structure. Form the selected lining or fill condition, with plating contact and metal distribution defined.
  5. Finish and route. Cu finishing, planarization, dielectric, and front- or back-face routing where included.
  6. Inspect and deliver. Dimensional, cross-section, and electrical checks as agreed, then wafer or diced coupon delivery.
Inspection and delivery

Check the feature that matters to your trial

Plan the sampling sites and any sacrificial coupons before the run. Electrical checks need a suitable pad and routing layout.

01

Via geometry and glass condition

Entry and exit dimensions, via profile, and visible edge or surface defects at identified fields.

02

Metallization and coverage

Layer measurements and cross-sections to evaluate the selected lining or fill condition.

03

Surface and handling

Topography, residual metal, bow, and the surface condition required by your next process.

04

Electrical connections

Continuity, resistance, or isolation using the defined test layout and access pads.

Delivery: hole-only, seeded, lined, filled, or routed structures as quoted, on full substrates or as diced, identified evaluation coupons.

Development programs

Glass test vehicles for materials and packaging teams

Glass and chemistry evaluation

Compare substrate grades, surface preparation, adhesion, and metallization on one defined via pattern.

Equipment and process trials

Repeatable coupons for drilling, seeding, plating, and planarization tool development.

Interposer architecture studies

Small routed prototypes to test pitch, routing density, and stack-up before committing to a full build.

Project questions

Define the glass flow before fabrication

Can I order only the glass with holes?

Yes. Hole-only coupons are a distinct delivery option. Include the glass grade, thickness, via pattern, entry and exit dimensions, cleanliness needs, and any requirement from your next process.

Can you metallize glass that has already been drilled?

Customer-supplied pre-drilled glass can be reviewed. Composition, hole profile, minimum internal diameter, surface condition, and handling format determine the suitable route.

What is the difference between a lined and a filled via?

A lined via has metal along the sidewall with an open centre; a filled via has a metal-filled core. They differ in fabrication, surface finishing, and integration, so state the intended condition.

Can the prototype include routing on both sides?

Double-face routing is reviewed together with the via and dielectric stack. Provide front- and back-face layouts, orientation conventions, pad finishes, alignment requirements, and test access.

How is via-fill quality verified?

The quotation defines the inspection method, sample count, locations, and acceptance criteria. Cross-sections characterize sampled vias; other methods depend on the glass and metal geometry.

Does an interposer prototype include the full package substrate?

The delivered stack is defined in the quotation. Build-up layers, bumps, die attach, and assembly can be added as further steps with their own requirements.

Start your project.
Response within one business day.

Share your process requirements, substrate, and production volume. A Nanosystems JP Inc. engineer will respond within one business day. Full quote typically within 7-10 business days, subject to project complexity and NDA requirements.

To help us review the glass flow, please include:
substrate type & size  ·  target process  ·  quantity  ·  timeline  ·  design files if available (not required for first review)

[email protected] · +81-3-5288-5569 · NDA available · All inquiries handled confidentially

Ready to discuss this process?
Technical review within one business day of inquiry. NDA available.
Request a Quote →
All Services
Full process flow →
Substrates
Substrate & WafersSi, SiC, GaN, glass, sapphire Fused Silica WafersQuartz · borosilicate · low CTE PI Film & SUS Sensor FabRoll-to-roll · sensor patterning
Front-End
Mask FabricationGDS to chrome mask, DRC PhotolithographyE-beam 20nm to 500×600mm NanoimprintingUV & thermal NIL Thin Film DepositionPVD, CVD, ALD, MBE LiftoffMetal pattern · shadow mask ElectroplatingCu TSV fill, DPC, LIGA EtchingICP-RIE, DRIE >50:1 AnnealingN₂/H₂/vacuum/RTA Ion ImplantationB/P/As/Al/N implant CMP & GrindingCu CMP, 50µm thinning DicingBlade, stealth laser Wafer CleaningRCA, plasma, megasonic
Advanced Packaging
Wafer BondingHybrid, eutectic, fusion TSV FabricationHigh AR, void-free Cu fill TSV RevealBackgrind → etch → CMP TGV FabricationThrough-glass via RDL FabricationBCB/PBO/PI + damascene Packaging & AssemblyWire bond, flip-chip 📚 3D/2.5D PackagingTSV+RDL+UBM+C4 AuSn BumpPVD lift-off, fluxless Indium BumpEvap lift-off · cryo/quantum UBM DepositionTi/Pt/Au · adhesion-barrier-Au Gold BumpEvap & plated · Au-Au TC AuGe / AuSi356/363°C eutectic die attach High-Pb Bumps95Pb5Sn · hi-rel C4 SLID / TLPCu/Sn · Au/In · Ag/In Al-Ge Sealing424°C · CMOS-friendly MEMS Ohmic ContactsGaAs · GaN · RTA + TLM Cryo & UHV MetallizationAuSn · Ti/Pd/Au · seal rings Optical AccessWindows · meshes · thru-holes MEMS Vapor CellsDRIE + bond · unfilled bodies Thin-Film-on-InsulatorQuartz-on-Si · LNOI Biochip & MicrofluidicsGlass 500×600mm, NIL SiPho PackagingTSV·RDL·UBM·C4 for PIC
Industries
AI & HPC PackagingCoWoS-style, 2.5D/3D Silicon PhotonicsSOI · AuSn · TSV interposer Quantum TechnologyIon traps · vapor cells · TFOI AutomotiveMEMS sensors, SiC power Life SciencesLab-on-chip, biosensors All Industries → Request a Quote →
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Services & Industries
Capabilities Overview
Substrates
Substrate & WafersSi, SiC, GaN, glass, sapphire Fused Silica WafersQuartz · borosilicate · low CTE PI Film & SUS Sensor FabRoll-to-roll · sensor patterning
Front-End
Mask FabricationGDS to chrome mask, DRC PhotolithographyE-beam 20 nm to 500×600 mm NanoimprintingUV & thermal NIL Thin Film DepositionPVD, CVD, ALD, MBE TFT & BackplaneIGZO · Glass · Display LiftoffMetal pattern · shadow mask ElectroplatingCu TSV fill, DPC, LIGA EtchingICP-RIE, DRIE >50:1 Microchannel CoolingEtched, bonded, heater test chips AnnealingN₂ / H₂ / vacuum / RTA Ion ImplantationB / P / As / Al / N implant CMP & GrindingCu CMP, 50 µm thinning Patterned Test WafersCustom CMP and process evaluation wafers DicingBlade, stealth laser Wafer CleaningRCA, plasma, megasonic
Advanced Packaging
Wafer BondingHybrid, eutectic, fusion TSV FabricationHigh AR, void-free Cu fill TSV RevealBackgrind → etch → CMP TGV FabricationThrough-glass via Glass TGV CouponsHole-only to routed prototypes RDL FabricationBCB / PBO / PI + damascene Packaging & AssemblyWire bond, flip-chip 3D / 2.5D PackagingTSV + RDL + UBM + C4 AuSn BumpPVD lift-off, fluxless Laser SubmountsSi/AlN submounts, optical benches Indium BumpEvap lift-off · cryo/quantum UBM DepositionTi/Pt/Au · adhesion-barrier-Au Cu Pillar & SnAg BumpingPillars with SnAg caps, SnAg bumps Gold BumpEvap & plated · Au-Au TC AuGe / AuSi356/363°C eutectic die attach High-Pb Bumps95Pb5Sn · hi-rel C4 SLID / TLPCu/Sn · Au/In · Ag/In Al-Ge Sealing424°C · CMOS-friendly MEMS Ohmic ContactsGaAs · GaN · RTA + TLM Cryo / UHV MetalAuSn · Ti/Pd/Au · rings Optical AccessWindows · meshes · holes Vapor CellsDRIE + bond · unfilled TFOI WafersQuartz-on-Si · LNOI Biochip & MicrofluidicsGlass 500×600 mm, NIL SiPho PackagingTSV · RDL · UBM · C4 for PIC
Industries
AI & HPC PackagingCoWoS-style, 2.5D / 3D Silicon PhotonicsSOI · AuSn · TSV interposer AutomotiveMEMS sensors, SiC power Life SciencesLab-on-chip, biosensors All Industries → Request a Quote →