Photonics packaging

Laser Submounts
and Silicon Optical Benches

Si and AlN submounts, silicon optical benches with V-grooves and recesses, patterned metallization, and AuSn-ready pads. Ordered bare, metallized, or solder-coated, with the mechanical and metal drawings reviewed together.

AuSn bump services →

Si and AlN submountsV-groovesRecesses and stepsPatterned metalAuSn optionsBare or solder-ready
Si / AlN
Substrate materials
per thermal design
V-groove
Fiber placement
reviewed per diameter
Au / AuSn
Pad finish and
solder options
Bare → solder
Delivered in the
condition you need
What you can order

The physical platform for your optical design

Order a standalone component, or discuss selected assembly steps. Mechanical reference surfaces and metal interfaces are reviewed alongside your device drawing.

V-groove for fiberrecess and stepmetallized die padAuSn readySchematic; V-groove geometry is set by crystal orientation and fiber diameter.
01

Laser and photonic submounts

Die-attach pads and electrical connection areas, front- and back-face metal reviewed together, with thermal path, electrical isolation, and assembly constraints considered.

02

Silicon optical benches

V-grooves for fiber placement subject to geometry and crystal orientation; recesses, steps, cavities, and alignment marks; wet-etch or DRIE routes selected for the feature shape.

03

Metallized and solder-ready parts

Au-finished pads and selected AuSn layer or bump options, with pad geometry reviewed against the die backside metal and the attachment method.

Design and feasibility

Bring the mechanical and metal drawings together

A useful inquiry describes the finished component and the parts that will mount to it. The fabrication route is reviewed against those interfaces.

ParameterWhat to include in your inquiry
Material and part formatSi or AlN, grade or orientation where relevant, part dimensions, thickness, surface finish, and quantity.
Mechanical featuresDimensioned drawing for grooves, cavities, steps, mounting areas, through-features, and dicing lines.
Optical reference geometryFiber diameter and pitch, intended groove engagement, die mounting height, and optical-axis offsets with their datums.
Metallization and solderPad layout, adhesion and barrier preferences, metal thicknesses, backside metal, insulation, and solder requirement.
Assembly conditionsMating die material and backside stack, attachment method, permitted process temperature, and handling limits.
Delivery and acceptanceBare etched, metallized, solder-coated, or assembled condition; dimensional and film inspection requirements.
Coordinated fabrication

From the component drawing to your assembly line

The sequence is selected for the substrate and the required delivery condition. Silicon etching and AlN component processing use different routes.

  1. Review the interfaces. Mounting planes, grooves, optical references, pad positions, mating materials, and the assembly that follows.
  2. Prepare the substrate. Select or receive the material and confirm thickness, orientation, surface condition, and handling.
  3. Form the features. Produce the agreed mechanical features; for silicon, anisotropic wet etching or DRIE according to the shape required.
  4. Pattern the metal. Form the specified insulation and adhesion, barrier, and surface-metal sequence, including solder layers where required.
  5. Singulate and finish. Dice or otherwise finish the parts, with edge quality and protected surfaces considered.
  6. Inspect and deliver. Check the defined dimensions and film features, then package components or proceed to separately agreed assembly.
Inspection and delivery

Verify the interfaces before mounting the die

Inspection is tied to the component drawing. State which dimensions and surfaces control your next assembly step.

01

Mechanical geometry

Groove, recess, step-height, thickness, and outline measurements relative to the specified datums.

02

Metal pattern and stack

Pad placement, pattern dimensions, and agreed film-thickness measurements; further stack checks on request.

03

Surface and edge condition

Visual checks for exposed surfaces, singulation edges, contamination, and handling-sensitive features.

04

Assembly evaluation

Where assembly is included, the inspection method and any optical, thermal, or electrical evaluation are defined in advance.

Delivery: bare structured silicon benches or prepared submounts, metallized or AuSn-coated components as quoted, identified parts with the agreed dimensional and film data, and optional die-attach or packaging work reviewed with your components.

Optical integration

Custom components for photonics development

Laser and emitter modules

Submounts and attachment interfaces for customer laser dies, emitters, and package components.

Fiber and PIC assemblies

Benches that hold fiber and photonic chips in a defined mechanical relationship.

Sensing and research optics

Small quantities of custom platforms for instruments and laboratory systems.

Project questions

Before you finalize the drawing

How do I choose between silicon and AlN?

Start with the thermal path, electrical isolation, feature geometry, expansion requirements, and metallization needs. Silicon suits lithographically defined mechanical features; AlN suits high thermal conductivity with electrical isolation.

Can you make V-grooves for my fiber diameter?

A silicon V-groove is reviewed from the fiber diameter, pitch, target centre height, and required contact geometry. Crystal orientation and the wet-etch route constrain the groove angle.

Can the part include AuSn for die attachment?

Selected AuSn layers or bump structures are reviewed with the pad stack and the die backside metal. Solder amount, barrier layers, wettable area, and the intended bonding profile are defined together.

Can I supply my own submounts for metallization?

Customer-supplied Si or AlN parts can be reviewed. Provide dimensions, material details, surface finish, existing films, cleanliness history, and available handling area.

Does a finished bench guarantee optical alignment?

The component is inspected against the agreed mechanical drawing. Final alignment and coupling depend on the fiber, active die, attachment layers, fixtures, and assembly method.

Can I buy only the passive components?

Yes. Bare structures, metallized parts, and solder-coated components are scoped as standalone deliverables; active dies, fibers, attachment, and packaging only where separately agreed.

Start your project.
Response within one business day.

Share your process requirements, substrate, and production volume. A Nanosystems JP Inc. engineer will respond within one business day. Full quote typically within 7-10 business days, subject to project complexity and NDA requirements.

To help us review your component drawing, please include:
substrate type & size  ·  target process  ·  quantity  ·  timeline  ·  design files if available (not required for first review)

[email protected] · +81-3-5288-5569 · NDA available on request

Ready to discuss this process?
Technical review within one business day of inquiry. NDA available.
Request a Quote →
All Services
Full process flow →
Substrates
Substrate & WafersSi, SiC, GaN, glass, sapphire Fused Silica WafersQuartz · borosilicate · low CTE PI Film & SUS Sensor FabRoll-to-roll · sensor patterning
Front-End
Mask FabricationGDS to chrome mask, DRC PhotolithographyE-beam 20nm to 500×600mm NanoimprintingUV & thermal NIL Thin Film DepositionPVD, CVD, ALD, MBE LiftoffMetal pattern · shadow mask ElectroplatingCu TSV fill, DPC, LIGA EtchingICP-RIE, DRIE >50:1 AnnealingN₂/H₂/vacuum/RTA Ion ImplantationB/P/As/Al/N implant CMP & GrindingCu CMP, 50µm thinning DicingBlade, stealth laser Wafer CleaningRCA, plasma, megasonic
Advanced Packaging
Wafer BondingHybrid, eutectic, fusion TSV FabricationHigh AR, void-free Cu fill TSV RevealBackgrind → etch → CMP TGV FabricationThrough-glass via RDL FabricationBCB/PBO/PI + damascene Packaging & AssemblyWire bond, flip-chip 📚 3D/2.5D PackagingTSV+RDL+UBM+C4 AuSn BumpPVD lift-off, fluxless Indium BumpEvap lift-off · cryo/quantum UBM DepositionTi/Pt/Au · adhesion-barrier-Au Gold BumpEvap & plated · Au-Au TC AuGe / AuSi356/363°C eutectic die attach High-Pb Bumps95Pb5Sn · hi-rel C4 SLID / TLPCu/Sn · Au/In · Ag/In Al-Ge Sealing424°C · CMOS-friendly MEMS Ohmic ContactsGaAs · GaN · RTA + TLM Cryo & UHV MetallizationAuSn · Ti/Pd/Au · seal rings Optical AccessWindows · meshes · thru-holes MEMS Vapor CellsDRIE + bond · unfilled bodies Thin-Film-on-InsulatorQuartz-on-Si · LNOI Biochip & MicrofluidicsGlass 500×600mm, NIL SiPho PackagingTSV·RDL·UBM·C4 for PIC
Industries
AI & HPC PackagingCoWoS-style, 2.5D/3D Silicon PhotonicsSOI · AuSn · TSV interposer Quantum TechnologyIon traps · vapor cells · TFOI AutomotiveMEMS sensors, SiC power Life SciencesLab-on-chip, biosensors All Industries → Request a Quote →
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Services & Industries
Capabilities Overview
Substrates
Substrate & WafersSi, SiC, GaN, glass, sapphire Fused Silica WafersQuartz · borosilicate · low CTE PI Film & SUS Sensor FabRoll-to-roll · sensor patterning
Front-End
Mask FabricationGDS to chrome mask, DRC PhotolithographyE-beam 20 nm to 500×600 mm NanoimprintingUV & thermal NIL Thin Film DepositionPVD, CVD, ALD, MBE TFT & BackplaneIGZO · Glass · Display LiftoffMetal pattern · shadow mask ElectroplatingCu TSV fill, DPC, LIGA EtchingICP-RIE, DRIE >50:1 Microchannel CoolingEtched, bonded, heater test chips AnnealingN₂ / H₂ / vacuum / RTA Ion ImplantationB / P / As / Al / N implant CMP & GrindingCu CMP, 50 µm thinning Patterned Test WafersCustom CMP and process evaluation wafers DicingBlade, stealth laser Wafer CleaningRCA, plasma, megasonic
Advanced Packaging
Wafer BondingHybrid, eutectic, fusion TSV FabricationHigh AR, void-free Cu fill TSV RevealBackgrind → etch → CMP TGV FabricationThrough-glass via Glass TGV CouponsHole-only to routed prototypes RDL FabricationBCB / PBO / PI + damascene Packaging & AssemblyWire bond, flip-chip 3D / 2.5D PackagingTSV + RDL + UBM + C4 AuSn BumpPVD lift-off, fluxless Laser SubmountsSi/AlN submounts, optical benches Indium BumpEvap lift-off · cryo/quantum UBM DepositionTi/Pt/Au · adhesion-barrier-Au Cu Pillar & SnAg BumpingPillars with SnAg caps, SnAg bumps Gold BumpEvap & plated · Au-Au TC AuGe / AuSi356/363°C eutectic die attach High-Pb Bumps95Pb5Sn · hi-rel C4 SLID / TLPCu/Sn · Au/In · Ag/In Al-Ge Sealing424°C · CMOS-friendly MEMS Ohmic ContactsGaAs · GaN · RTA + TLM Cryo / UHV MetalAuSn · Ti/Pd/Au · rings Optical AccessWindows · meshes · holes Vapor CellsDRIE + bond · unfilled TFOI WafersQuartz-on-Si · LNOI Biochip & MicrofluidicsGlass 500×600 mm, NIL SiPho PackagingTSV · RDL · UBM · C4 for PIC
Industries
AI & HPC PackagingCoWoS-style, 2.5D / 3D Silicon PhotonicsSOI · AuSn · TSV interposer AutomotiveMEMS sensors, SiC power Life SciencesLab-on-chip, biosensors All Industries → Request a Quote →