Patterned Test Wafers
and CMP Evaluation Substrates
Custom test wafers and coupons built around your experiment: your pattern, your film stack, delivered at the process stage you need, with the measurement plan agreed before the run. For CMP, plating, deposition, cleaning, and packaging development.
and diced coupons
for a first lot
your trial starts from
process baseline on file
Build the wafer around the question
Compare materials, map a process window, or prepare an equipment trial. You choose the starting structure and the stage at which fabrication stops.
Schematic. Pattern cells and placement are designed per program.
Patterned CMP test wafers
Line and space patterns, isolated features, and pad arrays in the metal and dielectric combinations your process uses; etched trenches, barrier and seed, or plated overburden ready for polishing; post-CMP samples with an agreed surface measurement plan.
Process and materials coupons
Customer-defined film stacks with reference areas, layouts for step coverage, residue, and dimensional inspection, delivered as full wafers or diced coupons where equipment allows.
Packaging test structures
Pad arrays, daisy chains, and via or bump fields for bonding, plating, and assembly trials, with identification marks that tie every measurement to a location.
Patterned Test Wafers and CMP Evaluation Substrates
Scope and specification options. Every figure is confirmed for your program in the quotation.
Define a useful experiment from the start
A drawing and a short description of what you want to compare are enough to begin. We review the substrate, pattern, and metrology requirements together and tell you what is missing.
| Parameter | What to include in your inquiry |
|---|---|
| Evaluation objective | The process or material under test, the comparison variables, the equipment interface, and whether the evaluation is a single trial or a repeating baseline. |
| Substrate and film stack | Wafer material, diameter, thickness, orientation where relevant, and each film material with its target thickness and the order of deposition. |
| Pattern definition | GDS or a dimensioned drawing with line width, space, pad size, trench depth, and local pattern density; mark the cells that carry the measurement. |
| Incoming and delivery stage | The starting wafer condition and the required endpoint: patterned dielectric, barrier and seed, metal overburden, or post-CMP. |
| Metrology and acceptance | Required dimensions, film thickness, topography, or electrical data, with the measurement method, scan window, and sampling locations. |
| Quantity and repeat runs | Number of wafers or coupons, process splits, sample identification, and whether repeat lots to the same baseline are expected. |
A controlled starting point for your trial
The sequence follows the delivery stage you choose. Mask revisions and process splits are fixed before the run so results stay comparable.
- 01Define the testAgree the comparison variables, the pattern cells that matter, the delivery condition, and the data the experiment needs.
- 02Review the layoutCheck GDS layers, pattern density, dimensions, reference marks, wafer orientation, and any equipment constraints.
- 03Prepare the stackSource or receive the substrate and form the agreed starting films, with incoming inspection recorded.
- 04Pattern and processRun the selected lithography, etching, deposition, and plating steps, applying the planned splits.
- 05Stop at your stageDeliver the intermediate structure, or continue through the defined polishing and cleaning steps.
- 06Inspect and identifyMeasure the agreed sites and deliver the lot with wafer IDs, layout revision, and the specified data.
Make the data traceable to the pattern
Define how each result will be measured before fabrication. A useful report connects the measurement to its location, pattern cell, and process condition.
Pattern geometry
Feature width, spacing, etch depth, and selected defect checks at identified test fields.
Films and overburden
Thickness and uniformity measurements by a method suited to the film and the pattern.
Post-CMP surface
Dishing, erosion, residual step height, or roughness, each with its reference plane and scan window stated.
Electrical structures
Continuity, resistance, or leakage checks where the layout provides test access.
Delivery: full wafers or identified coupons in the agreed process condition, with the layout revision, a wafer or coupon identification map, and the measurement data specified in the quotation.
Test substrates for the people improving the process
CMP consumables teams
Patterned substrates for slurry, pad, conditioner, and cleaning evaluations with the metal and dielectric features your customers actually polish.
Equipment developers
Repeatable wafers to the same baseline for tool qualification, chamber matching, and demonstration runs.
Packaging and research teams
Small lots of structures that would otherwise need a full mask set and a production line.
Before your next evaluation run
Do I need a complete GDS file to request a quote?
No. Start with the evaluation objective, substrate format, layer stack, and a sketch or dimensioned pattern description. Layout preparation and mask work can be included in the scope where required.
Can I order wafers before CMP and polish them myself?
Yes. Request a defined intermediate stage such as patterned dielectric, barrier and seed, or plated overburden, and include the incoming condition your polishing equipment requires.
How are dishing, erosion, and roughness specified?
They describe different surface properties. State the feature geometry, reference surface, measurement method, scan window, and sampling locations with your target; the quotation defines the acceptance criteria.
Can I reorder the same test pattern?
Repeat lots are quoted against an agreed layout revision, material stack, and process baseline. Tell us which variables must stay fixed and which you intend to change.
Are these stocked products?
No. This is a custom fabrication service. Available starting wafers, minimum quantities, mask requirements, and schedules are established during project review.
Processes usually combined with this work
Dedicated pages that start from this process
When the evaluation is about the interconnect rather than the wafer process, the daisy-chain die is the right vehicle.
Test wafers are often delivered bumped; this is the bump process they go through.
Start your project.
Response typically within one business day.
Share your process requirements, substrate, and production volume. A Nanosystems JP Inc. engineer will respond typically within one business day. Full quote typically within 7-10 business days, subject to project complexity and NDA requirements.