Process development

Patterned Test Wafers
and CMP Evaluation Substrates

Custom test wafers and coupons built around your experiment: your pattern, your film stack, delivered at the process stage you need, with the measurement plan agreed before the run. For CMP, plating, deposition, cleaning, and packaging development.

New to ordering from us? How it works →

CMP evaluationLine/space and pad arraysBarrier and seed stacksPlated overburdenCoupons or full wafersFrom 1 wafer
2-12 in
Wafer diameters
and diced coupons
1
Wafer minimum
for a first lot
Any stage
Delivered at the step
your trial starts from
Repeatable
Layout revision and
process baseline on file
What you can order

Build the wafer around the question

Compare materials, map a process window, or prepare an equipment trial. You choose the starting structure and the stage at which fabrication stops.

line / spacepad arraytrench fieldreferenceSchematic. Pattern cells and placement are designed per program.
01

Patterned CMP test wafers

Line and space patterns, isolated features, and pad arrays in the metal and dielectric combinations your process uses; etched trenches, barrier and seed, or plated overburden ready for polishing; post-CMP samples with an agreed surface measurement plan.

02

Process and materials coupons

Customer-defined film stacks with reference areas, layouts for step coverage, residue, and dimensional inspection, delivered as full wafers or diced coupons where equipment allows.

03

Packaging test structures

Pad arrays, daisy chains, and via or bump fields for bonding, plating, and assembly trials, with identification marks that tie every measurement to a location.

Design and feasibility

Define a useful experiment from the start

A drawing and a short description of what you want to compare are enough to begin. We review the substrate, pattern, and metrology requirements together and tell you what is missing.

ParameterWhat to include in your inquiry
Evaluation objectiveThe process or material under test, the comparison variables, the equipment interface, and whether the evaluation is a single trial or a repeating baseline.
Substrate and film stackWafer material, diameter, thickness, orientation where relevant, and each film material with its target thickness and the order of deposition.
Pattern definitionGDS or a dimensioned drawing with line width, space, pad size, trench depth, and local pattern density; mark the cells that carry the measurement.
Incoming and delivery stageThe starting wafer condition and the required endpoint: patterned dielectric, barrier and seed, metal overburden, or post-CMP.
Metrology and acceptanceRequired dimensions, film thickness, topography, or electrical data, with the measurement method, scan window, and sampling locations.
Quantity and repeat runsNumber of wafers or coupons, process splits, sample identification, and whether repeat lots to the same baseline are expected.
From layout to test lot

A controlled starting point for your trial

The sequence follows the delivery stage you choose. Mask revisions and process splits are fixed before the run so results stay comparable.

  1. Define the test. Agree the comparison variables, the pattern cells that matter, the delivery condition, and the data the experiment needs.
  2. Review the layout. Check GDS layers, pattern density, dimensions, reference marks, wafer orientation, and any equipment constraints.
  3. Prepare the stack. Source or receive the substrate and form the agreed starting films, with incoming inspection recorded.
  4. Pattern and process. Run the selected lithography, etching, deposition, and plating steps, applying the planned splits.
  5. Stop at your stage. Deliver the intermediate structure, or continue through the defined polishing and cleaning steps.
  6. Inspect and identify. Measure the agreed sites and deliver the lot with wafer IDs, layout revision, and the specified data.
Inspection and delivery

Make the data traceable to the pattern

Define how each result will be measured before fabrication. A useful report connects the measurement to its location, pattern cell, and process condition.

01

Pattern geometry

Feature width, spacing, etch depth, and selected defect checks at identified test fields.

02

Films and overburden

Thickness and uniformity measurements by a method suited to the film and the pattern.

03

Post-CMP surface

Dishing, erosion, residual step height, or roughness, each with its reference plane and scan window stated.

04

Electrical structures

Continuity, resistance, or leakage checks where the layout provides test access.

Delivery: full wafers or identified coupons in the agreed process condition, with the layout revision, a wafer or coupon identification map, and the measurement data specified in the quotation.

Who this supports

Test substrates for the people improving the process

CMP consumables teams

Patterned substrates for slurry, pad, conditioner, and cleaning evaluations with the metal and dielectric features your customers actually polish.

Equipment developers

Repeatable wafers to the same baseline for tool qualification, chamber matching, and demonstration runs.

Packaging and research teams

Small lots of structures that would otherwise need a full mask set and a production line.

Project questions

Before your next evaluation run

Do I need a complete GDS file to request a quote?

No. Start with the evaluation objective, substrate format, layer stack, and a sketch or dimensioned pattern description. Layout preparation and mask work can be included in the scope where required.

Can I order wafers before CMP and polish them myself?

Yes. Request a defined intermediate stage such as patterned dielectric, barrier and seed, or plated overburden, and include the incoming condition your polishing equipment requires.

How are dishing, erosion, and roughness specified?

They describe different surface properties. State the feature geometry, reference surface, measurement method, scan window, and sampling locations with your target; the quotation defines the acceptance criteria.

Can I reorder the same test pattern?

Repeat lots are quoted against an agreed layout revision, material stack, and process baseline. Tell us which variables must stay fixed and which you intend to change.

Are these stocked products?

No. This is a custom fabrication service. Available starting wafers, minimum quantities, mask requirements, and schedules are established during project review.

Start your project.
Response within one business day.

Share your process requirements, substrate, and production volume. A Nanosystems JP Inc. engineer will respond within one business day. Full quote typically within 7-10 business days, subject to project complexity and NDA requirements.

To help us define the experiment, please include:
substrate type & size  ·  target process  ·  quantity  ·  timeline  ·  design files if available (not required for first review)

[email protected] · +81-3-5288-5569 · NDA available

Ready to discuss this process?
Technical review within one business day of inquiry. NDA available.
Request a Quote →
All Services
Full process flow →
Substrates
Substrate & WafersSi, SiC, GaN, glass, sapphire Fused Silica WafersQuartz · borosilicate · low CTE PI Film & SUS Sensor FabRoll-to-roll · sensor patterning
Front-End
Mask FabricationGDS to chrome mask, DRC PhotolithographyE-beam 20nm to 500×600mm NanoimprintingUV & thermal NIL Thin Film DepositionPVD, CVD, ALD, MBE LiftoffMetal pattern · shadow mask ElectroplatingCu TSV fill, DPC, LIGA EtchingICP-RIE, DRIE >50:1 AnnealingN₂/H₂/vacuum/RTA Ion ImplantationB/P/As/Al/N implant CMP & GrindingCu CMP, 50µm thinning DicingBlade, stealth laser Wafer CleaningRCA, plasma, megasonic
Advanced Packaging
Wafer BondingHybrid, eutectic, fusion TSV FabricationHigh AR, void-free Cu fill TSV RevealBackgrind → etch → CMP TGV FabricationThrough-glass via RDL FabricationBCB/PBO/PI + damascene Packaging & AssemblyWire bond, flip-chip 📚 3D/2.5D PackagingTSV+RDL+UBM+C4 AuSn BumpPVD lift-off, fluxless Indium BumpEvap lift-off · cryo/quantum UBM DepositionTi/Pt/Au · adhesion-barrier-Au Gold BumpEvap & plated · Au-Au TC AuGe / AuSi356/363°C eutectic die attach High-Pb Bumps95Pb5Sn · hi-rel C4 SLID / TLPCu/Sn · Au/In · Ag/In Al-Ge Sealing424°C · CMOS-friendly MEMS Ohmic ContactsGaAs · GaN · RTA + TLM Cryo & UHV MetallizationAuSn · Ti/Pd/Au · seal rings Optical AccessWindows · meshes · thru-holes MEMS Vapor CellsDRIE + bond · unfilled bodies Thin-Film-on-InsulatorQuartz-on-Si · LNOI Biochip & MicrofluidicsGlass 500×600mm, NIL SiPho PackagingTSV·RDL·UBM·C4 for PIC
Industries
AI & HPC PackagingCoWoS-style, 2.5D/3D Silicon PhotonicsSOI · AuSn · TSV interposer Quantum TechnologyIon traps · vapor cells · TFOI AutomotiveMEMS sensors, SiC power Life SciencesLab-on-chip, biosensors All Industries → Request a Quote →
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Services & Industries
Capabilities Overview
Substrates
Substrate & WafersSi, SiC, GaN, glass, sapphire Fused Silica WafersQuartz · borosilicate · low CTE PI Film & SUS Sensor FabRoll-to-roll · sensor patterning
Front-End
Mask FabricationGDS to chrome mask, DRC PhotolithographyE-beam 20 nm to 500×600 mm NanoimprintingUV & thermal NIL Thin Film DepositionPVD, CVD, ALD, MBE TFT & BackplaneIGZO · Glass · Display LiftoffMetal pattern · shadow mask ElectroplatingCu TSV fill, DPC, LIGA EtchingICP-RIE, DRIE >50:1 Microchannel CoolingEtched, bonded, heater test chips AnnealingN₂ / H₂ / vacuum / RTA Ion ImplantationB / P / As / Al / N implant CMP & GrindingCu CMP, 50 µm thinning Patterned Test WafersCustom CMP and process evaluation wafers DicingBlade, stealth laser Wafer CleaningRCA, plasma, megasonic
Advanced Packaging
Wafer BondingHybrid, eutectic, fusion TSV FabricationHigh AR, void-free Cu fill TSV RevealBackgrind → etch → CMP TGV FabricationThrough-glass via Glass TGV CouponsHole-only to routed prototypes RDL FabricationBCB / PBO / PI + damascene Packaging & AssemblyWire bond, flip-chip 3D / 2.5D PackagingTSV + RDL + UBM + C4 AuSn BumpPVD lift-off, fluxless Laser SubmountsSi/AlN submounts, optical benches Indium BumpEvap lift-off · cryo/quantum UBM DepositionTi/Pt/Au · adhesion-barrier-Au Cu Pillar & SnAg BumpingPillars with SnAg caps, SnAg bumps Gold BumpEvap & plated · Au-Au TC AuGe / AuSi356/363°C eutectic die attach High-Pb Bumps95Pb5Sn · hi-rel C4 SLID / TLPCu/Sn · Au/In · Ag/In Al-Ge Sealing424°C · CMOS-friendly MEMS Ohmic ContactsGaAs · GaN · RTA + TLM Cryo / UHV MetalAuSn · Ti/Pd/Au · rings Optical AccessWindows · meshes · holes Vapor CellsDRIE + bond · unfilled TFOI WafersQuartz-on-Si · LNOI Biochip & MicrofluidicsGlass 500×600 mm, NIL SiPho PackagingTSV · RDL · UBM · C4 for PIC
Industries
AI & HPC PackagingCoWoS-style, 2.5D / 3D Silicon PhotonicsSOI · AuSn · TSV interposer AutomotiveMEMS sensors, SiC power Life SciencesLab-on-chip, biosensors All Industries → Request a Quote →