Advanced packaging

Cu Pillar and SnAg
Microbump Fabrication

Copper pillars with SnAg caps and SnAg solder microbumps on your wafers or dies: UBM, plating, and inspection defined around your pad stack, pitch, and assembly conditions, delivered as-plated or reflowed.

UBM stacks →

Cu pillar + SnAg capSnAg microbumpsUBM stacksAs-plated or reflowedCustomer wafers reviewedEngineering lots
Your pitch
Pillar and bump geometry
reviewed per layout
As-plated or
reflowed
Delivery condition
agreed before the run
Wafer or die
Bumped wafers or
diced bumped dies
Eng. lots
Development quantities
reviewed
Bump structures

Choose the interconnect for your assembly flow

Define the pad layout, the stand-off you need, and the assembly conditions. Metallurgy and fabrication sequence are reviewed together with your incoming wafer and passivation.

pad and passivationUBMCu pillarbarrier + SnAg capreflowedSchematic cross sections; pillar diameter, height, and cap volume are defined per program.
01

Cu pillars with SnAg caps

UBM, copper pillar, barrier, and cap treated as one stack; pillar diameter, height, and cap volume reviewed against the array layout; reflowed or as-plated delivery agreed before fabrication.

02

SnAg solder microbumps

SnAg composition and bump formation route defined in the quotation; pad opening, solder volume, and spacing reviewed for the chosen geometry; bump-only delivery or assembly evaluation.

At a glance

Cu Pillar and SnAg Microbump Fabrication

Scope and specification options. Every figure is confirmed for your program in the quotation.

Your pitch
Pillar and bump geometry reviewed per layout
As-plated or
reflowed
Delivery condition agreed before the run
Wafer or die
Bumped wafers or diced bumped dies
Eng. lots
Development quantities reviewed
Cu pillar + SnAg cap
SnAg microbumps
UBM stacks
As-plated or reflowed
Customer wafers reviewed
Engineering lots
Design and feasibility

The parameters that define your build

Send the dimensions you need and the wafer you have. The quotation establishes the supported geometry, process scope, lot size, and inspection plan for that combination.

ParameterWhat to include in your inquiry
Substrate and formatMaterial, wafer diameter or die dimensions, thickness, bow, and any restriction on carriers or handling.
Array and pad layoutGDS or dimensioned drawing; bump pitch, diameter, count, edge clearance, and the arrangement across the die.
Pillar and solder geometryRequired pillar height and diameter, solder cap thickness or volume, and the target condition at delivery.
Pad, passivation, and UBMExisting pad metal and layer stack, passivation material and opening, surface topography, and any UBM preference.
Thermal and chemical limitsMaximum process temperature, restricted chemicals or metals, existing device layers, and handling constraints.
Delivery and acceptanceQuantity, delivery date, wafer or diced-die format, bump-only or assembly scope, and the data required.
Coordinated fabrication

From the pad to the finished bump

A representative plating flow. The actual traveler is defined after review of the device, pad stack, and requested delivery condition.

Process flow
01Layout and padreview02Surface preparationand UBM03Resist moldpatterning04Metal plating05Mold removal andfinish06Inspection anddelivery
  1. 01Layout and pad reviewBump placement, pad openings, passivation, wafer handling, and the intended connection to the mating part.
  2. 02Surface preparation and UBMPrepare the contact surface and form the selected adhesion, barrier, and seed layers within the device limits.
  3. 03Resist mold patterningPattern the plating mold for the specified bump diameter, pitch, and height; mold geometry and alignment reviewed.
  4. 04Metal platingBuild the selected Cu, barrier, and SnAg sequence, or the SnAg bump structure, by the agreed plating route.
  5. 05Mold removal and finishRemove resist and exposed seed layers; solder-cap reflow or further surface preparation where specified.
  6. 06Inspection and deliveryCheck the agreed geometry and surface condition, then deliver bumped wafers or proceed to dicing.
Inspection and delivery

Agree the measurements before the run

Select the checks your next process step needs. Destructive tests, electrical structures, and sacrificial samples are planned as part of the quotation.

01

Bump geometry and placement

Optical inspection and dimensional measurement of the array, including placement, missing bumps, and defects.

02

Height and coplanarity

Profilometry or another suitable height measurement at an agreed set of wafer or die locations.

03

Metallurgy and cross-section

Layer thickness, cross-section, or composition measurements where the program requires them.

04

Mechanical and electrical evaluation

Bump shear or daisy-chain evaluation where suitable samples, structures, and criteria are defined.

Delivery: bumped wafers in the agreed as-plated or reflowed condition, diced bumped dies subject to handling review, defined inspection data with lot identification, and optional flip-chip assembly evaluation quoted with the mating substrate.

Applications

Interconnects for demanding packaging projects

01

Chiplets and interposers

Fine-pitch connections for chiplet assembly, silicon and glass interposers, and redistribution layers.

02

Photonics and optoelectronics

Bumps for hybrid integration where placement accuracy and stand-off control the optical path.

03

MEMS, sensors, and imaging

Bumped wafers for stacked sensor assemblies and read-out integration.

Project questions

Before you send a layout

How do Cu pillars and SnAg solder bumps differ?

A Cu pillar uses a copper body to define most of the stand-off, with a solder cap forming the joint. A SnAg bump takes its joint shape from the solder volume, the wettable pad, and reflow, so the two behave differently at fine pitch.

Can you process customer-supplied wafers?

Yes, after review. Provide material, diameter, thickness, pad stack, passivation, surface topography, and process restrictions; completed device wafers need their thermal and chemical limits stated.

Can you support engineering quantities?

Development lots are reviewed case by case. Minimum quantity, mask requirements, and any process-development work depend on the material, geometry, and route.

Can bump fabrication include flip-chip assembly?

Assembly can be discussed as part of the project. The mating substrate, alignment requirements, assembly profile, underfill or encapsulation needs, and inspection criteria are reviewed beforehand.

Do I need to specify every process layer before contacting you?

No. A pad-stack description, bump drawing, target stand-off, quantity, and assembly requirement are enough to start a technical review.

Related processes

Processes usually combined with this work

UBM DepositionElectroplatingRDL FabricationPackaging & Assembly
Related service

UBM Deposition: the process most often combined with this work, run in the same program.

View page →
Detailed offerings

Dedicated pages that start from this process

Daisy-chain test dies →

Bumped test dies that let you evaluate the joint before the product wafer is committed.

Start your project.
Response typically within one business day.

Share your process requirements, substrate, and production volume. A Nanosystems JP Inc. engineer will respond typically within one business day. Full quote typically within 7-10 business days, subject to project complexity and NDA requirements.

To help us review your layout, please include:
substrate type & size  ·  target process  ·  quantity  ·  timeline  ·  design files if available (not required for first review)

sales@nanosystemsjp.co.jp · +81-3-5288-5569 · NDA available on request

Ready to discuss this process?
Technical review typically within one business day of inquiry. NDA available.
Request a Quote →
Services & Industries
Capabilities Overview
Substrates
Substrate & WafersSi, SiC, GaN, glass, sapphire Fused Silica WafersQuartz · borosilicate · low CTE Glass ProcessingDrilling, etching, polishing PI Film & SUS Sensor FabRoll-to-roll · sensor patterning
Front-End
Mask FabricationGDS to chrome mask, DRC PhotolithographyE-beam 20 nm to 500 × 600 mm NanoimprintingUV & thermal NIL Thin Film DepositionPVD, CVD, ALD, MBE ALD CoatingConformal oxides, nitrides PECVD DielectricsSiO₂, SiN, SiON, a-Si TFT & BackplaneIGZO · Glass · Display Lift-OffMetal pattern · shadow mask ElectroplatingCu TSV fill, DPC, LIGA Electroforming & LIGANi shims, meshes, microstructures EtchingICP-RIE, DRIE >50:1 ICP-RIE EtchingSi, oxide, III-V, SiC, quartz MEMS FoundrySensors, actuators, microfluidics Microchannel CoolingEtched, bonded, heater test chips Thermal Test ChipsHeater dies, multi-zone, RTD Temperature SensorsPt/NiCr RTDs, thermocouples AnnealingN₂ / H₂ / vacuum / RTA Ion ImplantationB / P / As / Al / N implant CMP & GrindingCu CMP, 50 µm thinning Wafer ThinningTo 50 µm on carriers Backside MetallizationTi/Ni/Ag, Ti/Ni/Au, Ti/Cu Patterned Test WafersCustom CMP and process evaluation wafers Daisy-Chain Test DiesDummy dies, chains, bump options DicingBlade, stealth laser Stealth & Laser Dicing300 mm Si and glass, SDBG Wafer CleaningRCA, plasma, megasonic Cleaning ChemistryPiranha, SC-1, SC-2, RCA
Advanced Packaging
Wafer BondingHybrid, eutectic, fusion Anodic BondingGlass to silicon, cavities MEMS Cap WafersCavities, ports, seal lands, bonded TSV FabricationHigh AR, Cu fill InterposersSi and glass, TSV/TGV + RDL TSV RevealBackgrind → etch → CMP TGV FabricationThrough-glass via Glass TGV CouponsHole-only to routed prototypes RDL FabricationBCB / PBO / PI + damascene Packaging & AssemblyWire bond, flip-chip Flip-Chip BondingTC, reflow, AuSn, underfill 3D / 2.5D PackagingTSV + RDL + UBM + C4 AuSn BumpPVD lift-off, fluxless Laser SubmountsSi/AlN submounts, optical benches Indium BumpEvap lift-off · cryo/quantum UBM DepositionTi/Pt/Au · adhesion-barrier-Au Cu Pillar & SnAg BumpingPillars with SnAg caps, SnAg bumps Gold BumpEvap & plated · Au-Au TC AuGe / AuSi361/363 °C eutectic die attach High-Pb Bumps95Pb5Sn · hi-rel C4 SLID / TLPCu/Sn · Au/In · Ag/In Al-Ge Sealing424 °C · CMOS-friendly MEMS Ohmic ContactsGaAs · GaN · RTA + TLM SiC ProcessingThinning, films, contacts, dicing GaN & III-VGaN, GaAs, InP processing Cryo / UHV MetalAuSn · Ti/Pd/Au · rings Optical AccessWindows · meshes · holes Vapor CellsDRIE + bond · unfilled TFOI WafersQuartz-on-Si · LNOI Biochip & MicrofluidicsGlass 500 × 600 mm, NIL SiPho PackagingTSV · RDL · UBM · C4 for PIC Photonic DevicesSiN/SOI waveguides, gratings
Industries
AI & HPC PackagingCoWoS-style, 2.5D / 3D Silicon PhotonicsSOI · AuSn · TSV interposer AutomotiveMEMS sensors, SiC power Life SciencesLab-on-chip, biosensors All Industries → Request a Quote →