Cu Pillar and SnAg
Microbump Fabrication
Copper pillars with SnAg caps and SnAg solder microbumps on your wafers or dies: UBM, plating, and inspection defined around your pad stack, pitch, and assembly conditions, delivered as-plated or reflowed.
reviewed per layout
reflowed
agreed before the run
diced bumped dies
reviewed
Choose the interconnect for your assembly flow
Define the pad layout, the stand-off you need, and the assembly conditions. Metallurgy and fabrication sequence are reviewed together with your incoming wafer and passivation.
Cu pillars with SnAg caps
UBM, copper pillar, barrier, and cap treated as one stack; pillar diameter, height, and cap volume reviewed against the array layout; reflowed or as-plated delivery agreed before fabrication.
SnAg solder microbumps
SnAg composition and bump formation route defined in the quotation; pad opening, solder volume, and spacing reviewed for the chosen geometry; bump-only delivery or assembly evaluation.
The parameters that define your build
Send the dimensions you need and the wafer you have. The quotation establishes the supported geometry, process scope, lot size, and inspection plan for that combination.
| Parameter | What to include in your inquiry |
|---|---|
| Substrate and format | Material, wafer diameter or die dimensions, thickness, bow, and any restriction on carriers or handling. |
| Array and pad layout | GDS or dimensioned drawing; bump pitch, diameter, count, edge clearance, and the arrangement across the die. |
| Pillar and solder geometry | Required pillar height and diameter, solder cap thickness or volume, and the target condition at delivery. |
| Pad, passivation, and UBM | Existing pad metal and layer stack, passivation material and opening, surface topography, and any UBM preference. |
| Thermal and chemical limits | Maximum process temperature, restricted chemicals or metals, existing device layers, and handling constraints. |
| Delivery and acceptance | Quantity, delivery date, wafer or diced-die format, bump-only or assembly scope, and the data required. |
From the pad to the finished bump
A representative plating flow. The actual traveler is defined after review of the device, pad stack, and requested delivery condition.
- Layout and pad review. Bump placement, pad openings, passivation, wafer handling, and the intended connection to the mating part.
- Surface preparation and UBM. Prepare the contact surface and form the selected adhesion, barrier, and seed layers within the device limits.
- Resist mold patterning. Pattern the plating mold for the specified bump diameter, pitch, and height; mold geometry and alignment reviewed.
- Metal plating. Build the selected Cu, barrier, and SnAg sequence, or the SnAg bump structure, by the agreed plating route.
- Mold removal and finish. Remove resist and exposed seed layers; solder-cap reflow or further surface preparation where specified.
- Inspection and delivery. Check the agreed geometry and surface condition, then deliver bumped wafers or proceed to dicing.
Agree the measurements before the run
Select the checks your next process step needs. Destructive tests, electrical structures, and sacrificial samples are planned as part of the quotation.
Bump geometry and placement
Optical inspection and dimensional measurement of the array, including placement, missing bumps, and defects.
Height and coplanarity
Profilometry or another suitable height measurement at an agreed set of wafer or die locations.
Metallurgy and cross-section
Layer thickness, cross-section, or composition measurements where the program requires them.
Mechanical and electrical evaluation
Bump shear or daisy-chain evaluation where suitable samples, structures, and criteria are defined.
Delivery: bumped wafers in the agreed as-plated or reflowed condition, diced bumped dies subject to handling review, defined inspection data with lot identification, and optional flip-chip assembly evaluation quoted with the mating substrate.
Interconnects for demanding packaging projects
Chiplets and interposers
Fine-pitch connections for chiplet assembly, silicon and glass interposers, and redistribution layers.
Photonics and optoelectronics
Bumps for hybrid integration where placement accuracy and stand-off control the optical path.
MEMS, sensors, and imaging
Bumped wafers for stacked sensor assemblies and read-out integration.
Before you send a layout
How do Cu pillars and SnAg solder bumps differ?
A Cu pillar uses a copper body to define most of the stand-off, with a solder cap forming the joint. A SnAg bump takes its joint shape from the solder volume, the wettable pad, and reflow, so the two behave differently at fine pitch.
Can you process customer-supplied wafers?
Yes, after review. Provide material, diameter, thickness, pad stack, passivation, surface topography, and process restrictions; completed device wafers need their thermal and chemical limits stated.
Can you support engineering quantities?
Development lots are reviewed case by case. Minimum quantity, mask requirements, and any process-development work depend on the material, geometry, and route.
Can bump fabrication include flip-chip assembly?
Assembly can be discussed as part of the project. The mating substrate, alignment requirements, assembly profile, underfill or encapsulation needs, and inspection criteria are reviewed beforehand.
Do I need to specify every process layer before contacting you?
No. A pad-stack description, bump drawing, target stand-off, quantity, and assembly requirement are enough to start a technical review.
Start your project.
Response within one business day.
Share your process requirements, substrate, and production volume. A Nanosystems JP Inc. engineer will respond within one business day. Full quote typically within 7-10 business days, subject to project complexity and NDA requirements.