At Nanosystems JP Inc., we deposit and pattern gold-germanium (AuGe 88/12) and gold-silicon (AuSi 97/3) eutectics, the fluxless, high-temperature die-attach metallurgies of GaAs, SiC, and hermetic package work, and the base of the AuGe/Ni/Au ohmic contact system for n-GaAs. These alloys have no practical plating chemistry, so they are evaporated as stacked layers and patterned by lift-off, exactly the discipline behind our AuSn flow. 4-12 inch wafers, from a single wafer.
The top of the solder ladder
AuSi 363°C and AuGe 356°C sit above AuSn 278°C and indium 157°C, so a die attached with AuGe or AuSi survives every downstream reflow in the assembly. One flow covers the whole ladder.
When a die must survive every reflow that follows it, run hot in service, or sit in a hermetic package for decades, the industry reaches for gold-based eutectics. Three properties keep AuGe and AuSi irreplaceable.
Melting at 356°C and 363°C, AuGe and AuSi joints stay solid through AuSn attach at 278°C, SnAg reflow around 250°C, and every rework cycle below. That makes them the first joint in multi-step assemblies, the die attach that everything else is built on top of, and the choice for devices whose junction temperatures would creep past ordinary solders' service limits.
Like AuSn, these gold-rich alloys bond without flux: no residue, no voiding from flux volatiles, and no cleaning chemistry inside a package that will be hermetically sealed. The joints are rigid, high-modulus, and thermally conductive, exactly what a power die or a hermetic header wants underneath it.
AuGe is more than die attach: alloyed AuGe/Ni/Au is the standard ohmic contact to n-type GaAs, the metallization under decades of MESFETs, HEMTs, and MMICs. We deposit the stack by evaporation and lift-off and can alloy it by rapid thermal annealing in the same flow, to your contact recipe.
Neither alloy has a practical plating chemistry, so both are built the AuSn way: alternating layers evaporated to the target composition, patterned by lift-off or deposited blanket on die backsides, homogenizing into the eutectic on the first melt.
| Parameter | AuGe (88/12) | AuSi (97/3) |
|---|---|---|
| Eutectic Temperature | 356°C | 363°C |
| Wafer Sizes | 4 inch (100mm), 6 inch (150mm), 8 inch (200mm), 12 inch (300mm) | |
| Substrates | GaAs, Si, SiC, InP; others on request | |
| Deposition | Stacked-layer evaporation; composition by layer thickness ratio | |
| Patterning | Lift-off (±0.5µm) or blanket backside | |
| Die-Attach Layer Thickness | 1-5µm typical | |
| Ohmic Contact Stack | AuGe/Ni/Au, 0.1-0.3µm typical | N/A |
| RTA Alloying | Available in flow, per recipe | N/A |
| Composition Verification | Layer thickness ratio at deposition | |
| Backside Processing | Thinned-wafer handling available | |
| Inspection | Profilometry + SEM standard; cross-section on request | |
| Minimum Lot | From 1 wafer, prototype to production on the same recipe | |
AuGe die attach for GaAs power amplifiers and MMICs in telecom, radar, and satellite hardware, the fluxless, high-hierarchy joint that hermetic microwave packages are built on, with thermal conduction the die's dissipation depends on.
Alloyed AuGe/Ni/Au ohmic contacts for MESFET, HEMT, and MMIC front-ends, evaporated, lift-off patterned, and RTA alloyed to your recipe, with the low, stable contact resistance decades of III-V manufacturing established.
Gold-eutectic die attach for SiC and other wide-bandgap devices whose junction temperatures overrun ordinary solders, keeping the joint solid and conductive where the device actually operates.
AuSi and AuGe attach into hermetic headers, TO cans, and ceramic packages, fluxless joints with nothing to outgas, in the package styles that space, defense, and sensing programs still qualify.
High-hierarchy eutectic attach for laser bars and LED arrays where subsequent AuSn or solder steps follow, the first, hottest joint in a multi-metallurgy optical assembly.
Gold-eutectic joints carry decades of qualification heritage in space and defense hardware. We support new builds and legacy-process reproduction from single-wafer lots with full process documentation.
Stacked-layer evaporation, layer-ratio composition control, lift-off patterning: the discipline proven on our AuSn flow runs these alloys the same way.
Backside die-attach metallization and front-side AuGe/Ni/Au contacts, with RTA alloying, run as one program instead of two separate procurements.
These metallurgies cannot be plated, and lines built around plating avoid them. Evaporation and lift-off are our native route, so AuGe and AuSi are standard work here, not exceptions.
We ask what comes after this joint, AuSn, SnAg, rework, and place your attach at the right rung of the ladder, with the companion metallurgies available on the same UBM.
GaAs and InP wafers, thinned backsides, and fragile die-attach-ready substrates are handled with adapted chucking and thermal budgets, the routine case in this application space.
Prototype on a single wafer, verify composition and wetting, then scale on the same recipe with the prototype data as baseline. No re-qualification required.
Share your process requirements, substrate, and production volume. A Nanosystems JP Inc. engineer will respond within 24 hours. Full quote typically within 7-10 business days, subject to project complexity and NDA requirements.