At Nanosystems JP Inc., we deposit engineered bilayer stacks for solid-liquid interdiffusion bonding, also called transient liquid phase or IMC bonding: a thin low-melt interlayer of Sn or In, 1-3µm by design, over its high-melt matrix metal. Bond at 150-300°C at your line; the joint converts fully to intermetallic and remelts only far above the bonding temperature. Evaporated and lift-off patterned for fine features, plated Cu/Sn for frames and volume. Deposit-ready wafers from a single wafer, bonding trials on request.
The one solder trick that breaks the ladder
Conventional metallurgies must melt above every later step. SLID inverts that: bond near the interlayer's low melting point, and the converted intermetallic joint then survives temperatures far above it, above AuSn, above SnAg, sometimes above the die-attach step that came first. Assemble low, operate high.
Solid-liquid interdiffusion is the metallurgy for assemblies that cannot be heated but must survive heat. Three properties make it work, and all three are set at deposition, which is exactly where we come in.
During bonding, the thin Sn or In interlayer melts and diffuses into the matrix metal, converting entirely to intermetallic compound. The joint that forms has no remaining low-melt phase, so its remelt temperature is the intermetallic's, hundreds of degrees above the bonding temperature. Power die bonded at 280°C run at junction temperatures no soft solder tolerates; stacks bonded at 180°C survive full SnAg reflow afterward.
Full conversion only happens if the interlayer is thin, 1-3µm against an adequate matrix reserve, and that ratio is the entire engineering of the joint. It must be set at deposition, not by a plating bath's whims, and 1-3µm is precisely the regime where evaporation and lift-off are most comfortable. We deposit matrix and interlayer in one pump-down, ratio fixed by layer thickness, patterned at ±0.5µm.
Evaporated stacks carry no bath residues and can be capped in vacuum against oxidation, so bonding runs fluxless with low voiding, the behavior hermetic seal frames and thermal-path die attach both demand. Fine patterned frames come off the lift-off route; wide frames and volume runs come off plated Cu/Sn. Same joint physics, route chosen by geometry and quantity.
Each system trades bonding temperature, cost, and conductivity differently. We deposit all three, recommend from your assembly flow, and ship deposit-ready; bonding runs at your line, with bonding trials on our side available on request.
| Parameter | Evaporated (Au/In, Ag/In, Cu/Sn) | Plated (Cu/Sn) |
|---|---|---|
| Wafer Sizes | 4 inch (100mm), 6 inch (150mm), 8 inch (200mm), 12 inch (300mm) | |
| Substrates | Si, SiC, GaAs, InP, glass, sapphire; others on request | |
| Interlayer | Sn or In, 1-3µm typical, sized for full conversion | |
| Matrix | Cu, Au, or Ag | Cu |
| Bonding Window | ~150-300°C, system-dependent, at your bonder | |
| Post-Bond Stability | Cu-Sn >400°C; Au-In to ~540°C; Ag-In well above 300°C | |
| Patterning | Lift-off, ±0.5µm | Through-resist, ±1µm |
| Minimum Feature | ~5µm | ~20µm |
| Barriers & Caps | Ni barriers, Ti adhesion, Au caps on request | |
| Composition Verification | Cross-section on request | |
| Deliverable | Deposit-ready wafers; bonding trials on request | |
| Minimum Lot | From 1 wafer, prototype to production on the same recipe | |
Cu/Sn SLID for SiC and GaN power die whose junction temperatures overrun soft solders: bond at ~280°C, then operate where only the intermetallic survives, with the thermal path a converted, void-lean joint provides.
Patterned SLID frames for wafer-level hermetic sealing: bond within the MEMS thermal budget, and the sealed cavity then tolerates every downstream reflow. Fine frames by lift-off, wide frames plated.
Sub-200°C bonding for temperature-fragile optical assemblies and cryogenic hardware, with a joint that stays put through bake-outs and thermal cycling, alongside our indium bump flow on shared UBM.
Adding die to assemblies that already carry solder joints: SLID bonds below the existing metallurgy's melting point, then matches or exceeds its temperature rating, sidestepping the step-solder budget entirely.
Down-hole, engine-bay, and industrial electronics operating continuously above soft-solder limits, joined by intermetallics that treat 300°C as a service condition rather than a failure threshold.
Deposit-ready coupons and single wafers for SLID process development: your bonder, our stacks, with thickness-ratio series and cross-section analysis to dial in the conversion window.
Most SLID literature assumes you deposit your own stacks. We ship them engineered, verified, and ready for your bonder, the missing half of the process, solved.
Full conversion is a thickness-ratio calculation, and we treat it as one: interlayer and matrix sized per system, documented per lot.
Fine patterns go evaporated lift-off, frames and volume go plated Cu/Sn. Same physics, route chosen by your geometry and quantity, not our convenience.
Matrix on one wafer, interlayer on the other, or asymmetric sequences per your bond recipe, both halves processed in the same flow so they meet as designed.
Au/In runs beside indium bumping, Cu/Sn beside the plating line, all on shared UBM and lithography, managed end to end by a dedicated project manager.
Prototype the ratio on a single wafer, bond, cross-section, then scale on the same recipe with the data as baseline. No re-qualification required.
Share your process requirements, substrate, and production volume. A Nanosystems JP Inc. engineer will respond within 24 hours. Full quote typically within 7-10 business days, subject to project complexity and NDA requirements.