Wafer Thinning
and Temporary Bonding
Device wafers thinned to 50 µm and below on temporary carriers, or to 150-300 µm free-standing, with stress relief, backside metal and debonding in the same program. For TSV reveal, power devices, thin dies and stacked assemblies.
thickness, typical minimum
tolerance, typical
diameters
materials
Three ways to a thin wafer
Schematic; final thickness and bow control are agreed per program.
Free-standing thinning
Backgrinding and stress-relief polish to 150-300 µm without a carrier, for wafers that go on to standard dicing.
Temporary bonding and thinning
Adhesive bonding to a glass or silicon carrier, grinding to 50-100 µm, backside processing on the carrier, then laser, thermal or mechanical debond and clean.
TAIKO ring grinding
Thinning the wafer interior while leaving a support rim, for thin wafers that must be handled without a carrier.
Backside processing on carrier
TSV reveal, backside metallization, RDL and bumps while the wafer is supported. See TSV reveal.
Stress relief
Dry polish, CMP or wet etch after grinding to remove subsurface damage and control bow.
Thin-wafer dicing
Dicing on tape or frame after debonding, including stealth dicing for thin silicon.
Wafer Thinning and Temporary Bonding
Scope and specification options. Every figure is confirmed for your program in the quotation.
Typical ranges
Achievable thickness and tolerance depend on wafer diameter, material and topography; the quotation states the values for your wafers.
| Parameter | Typical | Note |
|---|---|---|
| Final thickness | 50-100 µm on carrier; 150-300 µm free-standing | Thinner on inquiry |
| Thickness tolerance | ±5 µm typical after grinding; ±3 µm with polish | TTV reported per lot |
| Carrier | Glass (for laser debond) or silicon; adhesive per thermal budget | Customer process temperature limits respected |
| Materials | Si, SOI, SiC, GaN-on-Si, GaAs, glass | Brittle materials with dedicated parameters |
| Wafer size | 4 to 12 inch | Pieces for feasibility |
| Bow after thinning | Managed by stress relief and film balance | Target agreed per stack |
For a thinning quotation
| Item | What helps |
|---|---|
| Wafer | Material, diameter, incoming thickness, front-side topography and bump height |
| Target | Final thickness and tolerance, TTV, bow limit |
| Constraints | Maximum process temperature, chemicals to avoid, protection of front-side structures |
| Backside work | Metal stack, reveal, RDL or bumps needed while on carrier |
| Quantity | Wafers and target date |
Processes usually combined with this work
Questions engineers ask before ordering
How thin can you go?
50 to 100 µm on a temporary carrier, 150 to 300 µm free-standing; thinner on inquiry.
Can you process the backside while the wafer is on the carrier?
Yes: TSV reveal, backside metallization, RDL and bumps before debonding.
What are the thermal limits?
Carrier and adhesive are chosen to your maximum process temperature; state it in the inquiry.
Start your project.
Initial response within one business day.
Share your process requirements, substrate, and production volume. A Nanosystems JP Inc. engineer gives an initial response, typically within one business day. A written quotation typically follows within 7-10 business days after we receive the required information and complete any prerequisite NDA.