Advanced packaging

Silicon and Glass
Interposer Prototyping

Through-via interposers for 2.5D integration, photonics and sensor read-out: TSV or TGV, redistribution on one or both faces, UBM and bumps, delivered as wafers or diced parts. Send your GDS and get a manufacturability review before anyone commits to a lot.

How ordering works →

TSV or TGVFront and back RDLUBM and bumpsGDS review firstFrom 1 waferWafer or diced
Si / glass
Core
materials
10 µm
Via diameter
from
1-2
RDL layers
per face
4-12 in
Wafer
formats
What we deliver

One program from via to bump

An interposer is a sequence of processes that each have their own page here. This page is where they are put together.

Top RDL and padsThrough viasBackside RDL / bumps

Schematic cross section. Via pitch, routing layers and bump type are set per design.

01

Silicon interposers

DRIE vias, insulating liner, barrier and seed, Cu fill and reveal, then damascene or semi-additive RDL. See TSV and RDL.

02

Glass interposers

Through-glass vias in borosilicate or alkali-free glass, lined or filled, with RDL on the metallized glass. See TGV and glass coupons.

03

Termination

UBM, Cu pillars with SnAg caps, solder or gold bumps sized to the mating die and substrate. See UBM and Cu pillar.

04

Dummy first

Where the layout is new, a dummy interposer with vias and daisy chains but no active routing qualifies the flow before the full design.

At a glance

Silicon and Glass Interposer Prototyping

Scope and specification options. Every figure is confirmed for your program in the quotation.

Si / glass
Core materials
10 µm
Via diameter from
1-2
RDL layers per face
4-12 in
Wafer formats
TSV or TGV
Front and back RDL
UBM and bumps
GDS review first
From 1 wafer
Wafer or diced
Capability

Typical design ranges

Ranges we quote routinely; combinations at the limits are reviewed on your layout.

ElementSiliconGlass
Via diameter5-50 µm typical20 µm and up; 50-100 µm routine
Substrate thickness100-400 µm after thinning; thick substrates to ~1.5 mm300 µm to 1 mm
Via pitchFrom 2× diameter, layout dependentFrom 2× diameter
Via fillFull Cu fill, void-free as verified by sampled cross sectionLined (open centre) or filled
RDL1-2 layers per face; damascene or semi-additive Cu1-2 layers per face on metallized glass
Line / space2/2 µm damascene; 5/5 µm semi-additive5/5 µm and up
Formats100-300 mm wafers100-200 mm wafers; panel on inquiry
How a program runs

GDS review to diced parts

Process flow
01Manufacturabilityreview02Test vehicle ordummy lot03Via formation andfill04Redistribution05Termination andsingulation06Delivery
  1. 01Manufacturability reviewVia sizes, pitches, keep-out zones, RDL rules and pad openings checked against the ranges above; a marked-up report comes back with the questions.
  2. 02Test vehicle or dummy lotFor a new layout, a short lot with vias and daisy chains proves fill, reveal and RDL before the full design runs.
  3. 03Via formation and fillDRIE or glass via formation, liner and barrier, seed and Cu fill, CMP.
  4. 04RedistributionFront-face RDL, temporary bonding and thinning where required, reveal and back-face RDL.
  5. 05Termination and singulationUBM and bumps, electrical test on daisy chains where designed in, dicing to your die size.
  6. 06DeliveryWafers or identified diced parts with the inspection data in the quotation.
What to send

For a manufacturability review

ItemWhat helps
GDSAll layers with a layer map; die size and count per wafer
Stack-upCore material and thickness, RDL layer count per face, dielectric preference, pad finish
Via and RDL rulesVia diameter and pitch, minimum line and space, keep-outs
Electrical needsDaisy chains or test structures for continuity, resistance and isolation
Quantity and stageDummy lot, prototype, pilot; wafer or diced delivery; target date
Direct answers

Questions engineers ask before ordering

Can you review my GDS before I order?

Yes. Via sizes, pitches, keep-outs, RDL rules and pad openings are checked and a marked-up report comes back before any quotation.

Silicon or glass?

Silicon for fine via pitch and damascene RDL; glass for RF, photonics and low-loss applications. Both are quoted on the same page.

Can you deliver diced interposers?

Yes, as identified diced parts with the inspection data agreed in the quotation.

Related service

TSV Fabrication: the process most often combined with this work, run in the same program.

View page →

Start your project.
Initial response within one business day.

Share your process requirements, substrate, and production volume. A Nanosystems JP Inc. engineer gives an initial response, typically within one business day. A written quotation typically follows within 7-10 business days after we receive the required information and complete any prerequisite NDA.

To speed up technical review, please include:
substrate type & size  ·  target process  ·  quantity  ·  timeline  ·  design files if available (not required for first review)

sales@nanosystemsjp.co.jp · +81-3-5288-5569 · NDA available · All inquiries handled confidentially

Ready to discuss this process?
Initial engineering response typically within one business day. NDA available on request.
Request a Quote →
All Services
Full process flow →
Substrates
Substrate & WafersSi, SiC, GaN, glass, sapphire Fused Silica WafersQuartz · borosilicate · low CTE PI Film & SUS Sensor FabRoll-to-roll · sensor patterning
Front-End
Mask FabricationGDS to chrome mask, DRC PhotolithographyE-beam 20nm to 500×600mm NanoimprintingUV & thermal NIL Thin Film DepositionPVD, CVD, ALD, MBE LiftoffMetal pattern · shadow mask ElectroplatingCu TSV fill, DPC, LIGA EtchingICP-RIE, DRIE >50:1 AnnealingN₂/H₂/vacuum/RTA Ion ImplantationB/P/As/Al/N implant CMP & GrindingCu CMP, 50µm thinning DicingBlade, stealth laser Wafer CleaningRCA, plasma, megasonic
Advanced Packaging
Wafer BondingHybrid, eutectic, fusion TSV FabricationHigh AR, void-free Cu fill TSV RevealBackgrind → etch → CMP TGV FabricationThrough-glass via RDL FabricationBCB/PBO/PI + damascene Packaging & AssemblyWire bond, flip-chip 📚 3D/2.5D PackagingTSV+RDL+UBM+C4 AuSn BumpPVD lift-off, fluxless Indium BumpEvap lift-off · cryo/quantum UBM DepositionTi/Pt/Au · adhesion-barrier-Au Gold BumpEvap & plated · Au-Au TC AuGe / AuSi356/363°C eutectic die attach High-Pb Bumps95Pb5Sn · hi-rel C4 SLID / TLPCu/Sn · Au/In · Ag/In Al-Ge Sealing424°C · CMOS-friendly MEMS Ohmic ContactsGaAs · GaN · RTA + TLM Cryo & UHV MetallizationAuSn · Ti/Pd/Au · seal rings Optical AccessWindows · meshes · thru-holes MEMS Vapor CellsDRIE + bond · unfilled bodies Thin-Film-on-InsulatorQuartz-on-Si · LNOI Biochip & MicrofluidicsGlass 500×600mm, NIL SiPho PackagingTSV·RDL·UBM·C4 for PIC
Industries
AI & HPC PackagingCoWoS-style, 2.5D/3D Silicon PhotonicsSOI · AuSn · TSV interposer Quantum TechnologyIon traps · vapor cells · TFOI AutomotiveMEMS sensors, SiC power Life SciencesLab-on-chip, biosensors All Industries → Request a Quote →
Technical AI - Nanosystems JP Inc.
AI assistant, replies instantly
Services & Industries
Capabilities Overview
Substrates
Substrate & WafersSi, SiC, GaN, glass, sapphire Fused Silica WafersQuartz · borosilicate · low CTE Glass ProcessingDrilling, etching, polishing PI Film & SUS Sensor FabRoll-to-roll · sensor patterning
Front-End
Mask FabricationGDS to chrome mask, DRC PhotolithographyE-beam 20 nm to 500×600 mm NanoimprintingUV & thermal NIL Thin Film DepositionPVD, CVD, ALD, MBE ALD CoatingConformal oxides, nitrides PECVD DielectricsSiO₂, SiN, SiON, a-Si TFT & BackplaneIGZO · Glass · Display LiftoffMetal pattern · shadow mask ElectroplatingCu TSV fill, DPC, LIGA Electroforming & LIGANi shims, meshes, microstructures EtchingICP-RIE, DRIE >50:1 MEMS FoundrySensors, actuators, microfluidics Microchannel CoolingEtched, bonded, heater test chips Thermal Test ChipsHeater dies, multi-zone, RTD Temperature SensorsPt/NiCr RTDs, thermocouples AnnealingN₂ / H₂ / vacuum / RTA Ion ImplantationB / P / As / Al / N implant CMP & GrindingCu CMP, 50 µm thinning Wafer ThinningTo 50 µm on carriers Patterned Test WafersCustom CMP and process evaluation wafers Daisy-Chain Test DiesDummy dies, chains, bump options DicingBlade, stealth laser Wafer CleaningRCA, plasma, megasonic
Advanced Packaging
Wafer BondingHybrid, eutectic, fusion Anodic BondingGlass to silicon, cavities MEMS Cap WafersCavities, ports, seal lands, bonded TSV FabricationHigh AR, void-free Cu fill InterposersSi and glass, TSV/TGV + RDL TSV RevealBackgrind → etch → CMP TGV FabricationThrough-glass via Glass TGV CouponsHole-only to routed prototypes RDL FabricationBCB / PBO / PI + damascene Packaging & AssemblyWire bond, flip-chip 3D / 2.5D PackagingTSV + RDL + UBM + C4 AuSn BumpPVD lift-off, fluxless Laser SubmountsSi/AlN submounts, optical benches Indium BumpEvap lift-off · cryo/quantum UBM DepositionTi/Pt/Au · adhesion-barrier-Au Cu Pillar & SnAg BumpingPillars with SnAg caps, SnAg bumps Gold BumpEvap & plated · Au-Au TC AuGe / AuSi356/363°C eutectic die attach High-Pb Bumps95Pb5Sn · hi-rel C4 SLID / TLPCu/Sn · Au/In · Ag/In Al-Ge Sealing424°C · CMOS-friendly MEMS Ohmic ContactsGaAs · GaN · RTA + TLM SiC ProcessingContacts, implant, 1800 °C anneal GaN & III-VGaN, GaAs, InP processing Cryo / UHV MetalAuSn · Ti/Pd/Au · rings Optical AccessWindows · meshes · holes Vapor CellsDRIE + bond · unfilled TFOI WafersQuartz-on-Si · LNOI Biochip & MicrofluidicsGlass 500×600 mm, NIL SiPho PackagingTSV · RDL · UBM · C4 for PIC
Industries
AI & HPC PackagingCoWoS-style, 2.5D / 3D Silicon PhotonicsSOI · AuSn · TSV interposer AutomotiveMEMS sensors, SiC power Life SciencesLab-on-chip, biosensors All Industries → Request a Quote →