MEMS packaging

MEMS Cavity and
Cap Wafer Fabrication

The lid for your MEMS device, made to your layout: silicon or glass cap wafers with etched cavities, through-ports, alignment features, seal lands and metallization, delivered on their own or bonded to your device wafer.

Anodic bonding →

Si and glass capsCavities and portsSeal lands and gettersAuSn, Al-Ge, anodic, fritAligned bondingFrom 1 wafer
4-8 in
Wafer
diameters
10-500 µm
Cavity depth
typical
±5 µm
Bond alignment
typical
1
Wafer minimum
order
What we build

Caps designed with the bond in mind

A cap wafer is specified by what it must seal, what must pass through it, and how it will be joined. We design all three together so the cap arrives ready for your bonder, or comes back already bonded.

Closed cavityPorted cavity (open until sealed)CapSeal lands (perimeter)Device wafer

Schematic section: the seal is formed on the two perimeter lands, not across the cavity mouth; a ported cavity is not hermetic until its closure step. Cavity size, seal type and port position are set per design.

01

Silicon caps

DRIE or KOH cavities to a defined depth, optional through-ports and vent holes, oxide or metal seal lands; thinned where the package height is tight.

02

Glass caps

Borosilicate glass caps can be reviewed for anodic bonding to silicon. Fused-silica caps are reviewed separately for a compatible bonding route, which may require an intermediate structure. Cavity geometry, seal lands and allowable thermal conditions are confirmed for the selected material pair; ports and cavities are made to the same layout. See glass processing.

03

Seal lands and getters

AuSn, Au, Al-Ge or glass-frit seal rings patterned to your bond frame; getter deposition in the cavity for vacuum packages on request.

04

Bonded delivery

Aligned wafer-level bonding to your device wafer by anodic, eutectic, thermocompression or frit routes, with hermeticity testing as agreed. See wafer bonding.

At a glance

MEMS Cavity and Cap Wafer Fabrication

Scope and specification options. Every figure is confirmed for your program in the quotation.

4-8 in
Wafer diameters
10-500 µm
Cavity depth typical
±5 µm
Bond alignment typical
1
Wafer minimum order
Si and glass caps
Cavities and ports
Seal lands and getters
AuSn, Al-Ge, anodic, frit
Aligned bonding
From 1 wafer
Specification

Typical ranges

ParameterTypicalNote
Cap materialSilicon 300-725 µm; borosilicate and fused silica 300-700 µmThinner caps on carriers
Cavity, siliconDepth 10-500 µm by Bosch DRIE or KOH; through-cavity where neededKOH profile depends on orientation and mask geometry
Cavity, glassWet etch, laser or ultrasonic machining in borosilicate or fused silicaProfile, depth and remaining thickness confirmed per glass and route
Ports and ventsThrough-holes from 50 µm; vent channels for controlled cavity pressureSealed after bonding on request
Seal landAuSn, Au, Al-Ge, glass frit, or bare for anodic and fusionRing width and metal stack per bond
AlignmentMarks for front-to-front and front-to-back; post-bond X/Y offset of ±5 µm is a typical target for reviewed substrate and bond-route pairsReference and pre- versus post-bond registration stated per program; tighter on request
Cavity atmosphereAir, nitrogen, or reduced pressure at bonding; getter on inquiryThe retained cavity pressure is specified as a target with its temperature, outgassing and measurement method; a ported cavity is not hermetic until its closure step
InspectionBond interface by IR or acoustic imaging and optical inspectionHermeticity or leak-rate testing is a separate agreed test with method, cavity size, sampling and criteria; cap-only delivery includes dimensional and film inspection unless more is agreed
DeliveryCap wafers alone, bonded stacks, or diced capped devicesDicing of bonded stacks reviewed
How a program runs

From layout to capped wafers

Process flow
01Define the cap02Layout03Fabricate the cap04Bond05Inspect and deliver
  1. 01Define the capCavity map, ports, seal type, bond route, delivery format.
  2. 02LayoutCap GDS aligned to your device layout; returned for approval.
  3. 03Fabricate the capEtch cavities and ports, form seal lands, deposit getter where specified.
  4. 04BondAligned bonding to your device wafer, or ship caps for your bonder.
  5. 05Inspect and deliverBond inspection and hermeticity as agreed; wafers or diced parts.
What to send

For a cap wafer quotation

ItemWhat helps
Device waferMaterial, size, topography under the seal ring, thermal budget
Cap layoutCavity positions and depth, device clearance and remaining roof thickness, ports, seal ring geometry and land roughness, marks, optical requirements
Bond routePreferred method or constraints, maximum process temperature and voltage, electrical feedthroughs, target cavity atmosphere
DeliveryCaps only, bonded, or bonded and diced
QuantityWafers and target date
Direct answers

Questions engineers ask before ordering

Can you bond the cap to my device wafer?

Yes, by anodic, eutectic, thermocompression or glass-frit routes, aligned to your marks, with hermeticity testing as agreed. Caps can also ship alone for your bonder.

Can the cavity hold vacuum?

Reduced-pressure sealing and getter deposition are available on inquiry. The retained pressure is specified as a target with its measurement method; getters need an activation budget and placement review.

What do you need to quote a cap wafer?

Device wafer material and size, topography under the seal ring, thermal budget, cavity map and depth, ports, seal ring geometry, bond route, delivery format, quantity and date.

Related processes

Processes usually combined with this work

Anodic BondingWafer BondingAl-Ge SealingDeep Silicon EtchingMEMS FoundryVapor Cells
Related service

Anodic Bonding: the process most often combined with this work, run in the same program.

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Start your project.
Initial response within one business day.

Share your process requirements, substrate, and production volume. A Nanosystems JP Inc. engineer gives an initial response, typically within one business day. A written quotation typically follows within 7-10 business days after we receive the required information and complete any prerequisite NDA.

To speed up technical review, please include:
substrate type & size  ·  target process  ·  quantity  ·  timeline  ·  design files if available (not required for first review)

sales@nanosystemsjp.co.jp · +81-3-5288-5569 · NDA available · All inquiries handled confidentially

Ready to discuss this process?
Initial engineering response typically within one business day. NDA available on request.
Request a Quote →
All Services
Full process flow →
Substrates
Substrate & WafersSi, SiC, GaN, glass, sapphire Fused Silica WafersQuartz · borosilicate · low CTE PI Film & SUS Sensor FabRoll-to-roll · sensor patterning
Front-End
Mask FabricationGDS to chrome mask, DRC PhotolithographyE-beam 20nm to 500×600mm NanoimprintingUV & thermal NIL Thin Film DepositionPVD, CVD, ALD, MBE LiftoffMetal pattern · shadow mask ElectroplatingCu TSV fill, DPC, LIGA EtchingICP-RIE, DRIE >50:1 AnnealingN₂/H₂/vacuum/RTA Ion ImplantationB/P/As/Al/N implant CMP & GrindingCu CMP, 50µm thinning DicingBlade, stealth laser Wafer CleaningRCA, plasma, megasonic
Advanced Packaging
Wafer BondingHybrid, eutectic, fusion TSV FabricationHigh AR, void-free Cu fill TSV RevealBackgrind → etch → CMP TGV FabricationThrough-glass via RDL FabricationBCB/PBO/PI + damascene Packaging & AssemblyWire bond, flip-chip 📚 3D/2.5D PackagingTSV+RDL+UBM+C4 AuSn BumpPVD lift-off, fluxless Indium BumpEvap lift-off · cryo/quantum UBM DepositionTi/Pt/Au · adhesion-barrier-Au Gold BumpEvap & plated · Au-Au TC AuGe / AuSi356/363°C eutectic die attach High-Pb Bumps95Pb5Sn · hi-rel C4 SLID / TLPCu/Sn · Au/In · Ag/In Al-Ge Sealing424°C · CMOS-friendly MEMS Ohmic ContactsGaAs · GaN · RTA + TLM Cryo & UHV MetallizationAuSn · Ti/Pd/Au · seal rings Optical AccessWindows · meshes · thru-holes MEMS Vapor CellsDRIE + bond · unfilled bodies Thin-Film-on-InsulatorQuartz-on-Si · LNOI Biochip & MicrofluidicsGlass 500×600mm, NIL SiPho PackagingTSV·RDL·UBM·C4 for PIC
Industries
AI & HPC PackagingCoWoS-style, 2.5D/3D Silicon PhotonicsSOI · AuSn · TSV interposer Quantum TechnologyIon traps · vapor cells · TFOI AutomotiveMEMS sensors, SiC power Life SciencesLab-on-chip, biosensors All Industries → Request a Quote →
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Capabilities Overview
Substrates
Substrate & WafersSi, SiC, GaN, glass, sapphire Fused Silica WafersQuartz · borosilicate · low CTE Glass ProcessingDrilling, etching, polishing PI Film & SUS Sensor FabRoll-to-roll · sensor patterning
Front-End
Mask FabricationGDS to chrome mask, DRC PhotolithographyE-beam 20 nm to 500×600 mm NanoimprintingUV & thermal NIL Thin Film DepositionPVD, CVD, ALD, MBE ALD CoatingConformal oxides, nitrides PECVD DielectricsSiO₂, SiN, SiON, a-Si TFT & BackplaneIGZO · Glass · Display LiftoffMetal pattern · shadow mask ElectroplatingCu TSV fill, DPC, LIGA Electroforming & LIGANi shims, meshes, microstructures EtchingICP-RIE, DRIE >50:1 MEMS FoundrySensors, actuators, microfluidics Microchannel CoolingEtched, bonded, heater test chips Thermal Test ChipsHeater dies, multi-zone, RTD Temperature SensorsPt/NiCr RTDs, thermocouples AnnealingN₂ / H₂ / vacuum / RTA Ion ImplantationB / P / As / Al / N implant CMP & GrindingCu CMP, 50 µm thinning Wafer ThinningTo 50 µm on carriers Patterned Test WafersCustom CMP and process evaluation wafers Daisy-Chain Test DiesDummy dies, chains, bump options DicingBlade, stealth laser Wafer CleaningRCA, plasma, megasonic
Advanced Packaging
Wafer BondingHybrid, eutectic, fusion Anodic BondingGlass to silicon, cavities MEMS Cap WafersCavities, ports, seal lands, bonded TSV FabricationHigh AR, void-free Cu fill InterposersSi and glass, TSV/TGV + RDL TSV RevealBackgrind → etch → CMP TGV FabricationThrough-glass via Glass TGV CouponsHole-only to routed prototypes RDL FabricationBCB / PBO / PI + damascene Packaging & AssemblyWire bond, flip-chip 3D / 2.5D PackagingTSV + RDL + UBM + C4 AuSn BumpPVD lift-off, fluxless Laser SubmountsSi/AlN submounts, optical benches Indium BumpEvap lift-off · cryo/quantum UBM DepositionTi/Pt/Au · adhesion-barrier-Au Cu Pillar & SnAg BumpingPillars with SnAg caps, SnAg bumps Gold BumpEvap & plated · Au-Au TC AuGe / AuSi356/363°C eutectic die attach High-Pb Bumps95Pb5Sn · hi-rel C4 SLID / TLPCu/Sn · Au/In · Ag/In Al-Ge Sealing424°C · CMOS-friendly MEMS Ohmic ContactsGaAs · GaN · RTA + TLM SiC ProcessingContacts, implant, 1800 °C anneal GaN & III-VGaN, GaAs, InP processing Cryo / UHV MetalAuSn · Ti/Pd/Au · rings Optical AccessWindows · meshes · holes Vapor CellsDRIE + bond · unfilled TFOI WafersQuartz-on-Si · LNOI Biochip & MicrofluidicsGlass 500×600 mm, NIL SiPho PackagingTSV · RDL · UBM · C4 for PIC
Industries
AI & HPC PackagingCoWoS-style, 2.5D / 3D Silicon PhotonicsSOI · AuSn · TSV interposer AutomotiveMEMS sensors, SiC power Life SciencesLab-on-chip, biosensors All Industries → Request a Quote →