Deposition

ALD Coating
Services

Atomic layer deposition for the layers that must be conformal: via liners, gate dielectrics, passivation, moisture barriers and diffusion barriers. Thermal and plasma-enhanced routes, from a few nanometres to a few hundred, on wafers up to 300 mm.

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Al₂O₃, HfO₂, ZrO₂TiO₂, SiO₂TiN, TaNThermal and plasma ALDHigh aspect ratioUp to 300 mm
1-300 nm
Thickness
range, typical
Conformal
Coverage in qualified
high-aspect-ratio features
80-300 °C
Deposition
temperature window
Up to 300 mm
Wafer
formats
Films and uses

Where ALD earns its place

Sequential, self-limiting surface reactions give thickness control by cycle count and coverage that sputtering cannot reach inside deep features. Growth per cycle depends on the material and process and is commonly a fraction of a monolayer.

Conformal ALD filmFeature sidewall and bottomSubstrate

Schematic; ALD follows topography, including via sidewalls and undercuts, where the geometry has been qualified.

🔬

Via and trench liners

Al₂O₃ or SiO₂ insulation liners inside TSV and TGV, TiN or TaN barriers under the Cu seed. See TSV.

⚙️

Gate dielectrics

HfO₂, Al₂O₃ and ZrO₂ for GaN HEMTs, oxide semiconductors and research transistors; interface preparation agreed per stack.

🧪

Passivation and encapsulation

Pinhole-free moisture barriers on MEMS, sensors and optical parts; low-temperature routes for polymer and III-V surfaces.

📐

Optical and index layers

TiO₂, Al₂O₃ and SiO₂ stacks for filters and AR coatings with cycle-accurate thickness.

🧩

Cladding and gap fill

Conformal SiO₂ over etched photonic structures where a gap must be filled without voids.

🔩

Metallic ALD

TiN, TaN and Ru layers as barriers, electrodes and seeds where step coverage matters.

At a glance

ALD Coating Services

Scope and specification options. Every figure is confirmed for your program in the quotation.

1-300 nm
Thickness range, typical
Conformal
Coverage in qualified high-aspect-ratio features
80-300 °C
Deposition temperature window
Up to 300 mm
Wafer formats
Al₂O₃, HfO₂, ZrO₂
TiO₂, SiO₂
TiN, TaN
Thermal and plasma ALD
High aspect ratio
Up to 300 mm
Capability

Typical ranges

ParameterTypicalNote
MaterialsAl₂O₃, HfO₂, ZrO₂, TiO₂, SiO₂, ZnO, TiN, TaN, RuOthers on inquiry
Thickness1-300 nmThickness set by cycle count; thicker by agreement
UniformityWithin-wafer thickness uniformity reported per lotMethod and sites agreed
Temperature80-300 °C thermal; plasma-enhanced at the low endSelected for your thermal budget
SubstratesSi, glass, III-V, polymers, patterned and etched wafers; pieces to 300 mmWafer formats; roll-to-roll ALD is not offered
ConformalityHigh conformality in qualified high-aspect-ratio geometriesConfirmed by cross section on your feature
What to send

For an ALD quotation

ItemWhat helps
FilmMaterial, target thickness and tolerance, refractive index or electrical requirement
SubstrateMaterial, size, surface condition, existing films and structures with aspect ratio
Thermal budgetMaximum temperature the wafer can see
InspectionEllipsometry, cross section, electrical test as required
QuantityPieces or wafers and target date
Related service

Thin Film Deposition: the process most often combined with this work, run in the same program.

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Direct answers

Questions engineers ask before ordering

Can you coat customer-supplied substrates?

Yes, silicon, glass, III-V, polymers and patterned or etched wafers, after a review of the surface and the thermal budget.

Which thickness range?

1 to 300 nm typical, set by cycle count; thicker by agreement.

Do you offer roll-to-roll ALD?

No. ALD runs on wafer and piece formats up to 300 mm.

Start your project.
Initial response within one business day.

Share your process requirements, substrate, and production volume. A Nanosystems JP Inc. engineer gives an initial response, typically within one business day. A written quotation typically follows within 7-10 business days after we receive the required information and complete any prerequisite NDA.

To speed up technical review, please include:
substrate type & size  ·  target process  ·  quantity  ·  timeline  ·  design files if available (not required for first review)

sales@nanosystemsjp.co.jp · +81-3-5288-5569 · NDA available · All inquiries handled confidentially

Ready to discuss this process?
Initial engineering response typically within one business day. NDA available on request.
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All Services
Full process flow →
Substrates
Substrate & WafersSi, SiC, GaN, glass, sapphire Fused Silica WafersQuartz · borosilicate · low CTE PI Film & SUS Sensor FabRoll-to-roll · sensor patterning
Front-End
Mask FabricationGDS to chrome mask, DRC PhotolithographyE-beam 20nm to 500×600mm NanoimprintingUV & thermal NIL Thin Film DepositionPVD, CVD, ALD, MBE LiftoffMetal pattern · shadow mask ElectroplatingCu TSV fill, DPC, LIGA EtchingICP-RIE, DRIE >50:1 AnnealingN₂/H₂/vacuum/RTA Ion ImplantationB/P/As/Al/N implant CMP & GrindingCu CMP, 50µm thinning DicingBlade, stealth laser Wafer CleaningRCA, plasma, megasonic
Advanced Packaging
Wafer BondingHybrid, eutectic, fusion TSV FabricationHigh AR, void-free Cu fill TSV RevealBackgrind → etch → CMP TGV FabricationThrough-glass via RDL FabricationBCB/PBO/PI + damascene Packaging & AssemblyWire bond, flip-chip 📚 3D/2.5D PackagingTSV+RDL+UBM+C4 AuSn BumpPVD lift-off, fluxless Indium BumpEvap lift-off · cryo/quantum UBM DepositionTi/Pt/Au · adhesion-barrier-Au Gold BumpEvap & plated · Au-Au TC AuGe / AuSi356/363°C eutectic die attach High-Pb Bumps95Pb5Sn · hi-rel C4 SLID / TLPCu/Sn · Au/In · Ag/In Al-Ge Sealing424°C · CMOS-friendly MEMS Ohmic ContactsGaAs · GaN · RTA + TLM Cryo & UHV MetallizationAuSn · Ti/Pd/Au · seal rings Optical AccessWindows · meshes · thru-holes MEMS Vapor CellsDRIE + bond · unfilled bodies Thin-Film-on-InsulatorQuartz-on-Si · LNOI Biochip & MicrofluidicsGlass 500×600mm, NIL SiPho PackagingTSV·RDL·UBM·C4 for PIC
Industries
AI & HPC PackagingCoWoS-style, 2.5D/3D Silicon PhotonicsSOI · AuSn · TSV interposer Quantum TechnologyIon traps · vapor cells · TFOI AutomotiveMEMS sensors, SiC power Life SciencesLab-on-chip, biosensors All Industries → Request a Quote →
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Capabilities Overview
Substrates
Substrate & WafersSi, SiC, GaN, glass, sapphire Fused Silica WafersQuartz · borosilicate · low CTE Glass ProcessingDrilling, etching, polishing PI Film & SUS Sensor FabRoll-to-roll · sensor patterning
Front-End
Mask FabricationGDS to chrome mask, DRC PhotolithographyE-beam 20 nm to 500×600 mm NanoimprintingUV & thermal NIL Thin Film DepositionPVD, CVD, ALD, MBE ALD CoatingConformal oxides, nitrides PECVD DielectricsSiO₂, SiN, SiON, a-Si TFT & BackplaneIGZO · Glass · Display LiftoffMetal pattern · shadow mask ElectroplatingCu TSV fill, DPC, LIGA Electroforming & LIGANi shims, meshes, microstructures EtchingICP-RIE, DRIE >50:1 MEMS FoundrySensors, actuators, microfluidics Microchannel CoolingEtched, bonded, heater test chips Thermal Test ChipsHeater dies, multi-zone, RTD Temperature SensorsPt/NiCr RTDs, thermocouples AnnealingN₂ / H₂ / vacuum / RTA Ion ImplantationB / P / As / Al / N implant CMP & GrindingCu CMP, 50 µm thinning Wafer ThinningTo 50 µm on carriers Patterned Test WafersCustom CMP and process evaluation wafers Daisy-Chain Test DiesDummy dies, chains, bump options DicingBlade, stealth laser Wafer CleaningRCA, plasma, megasonic
Advanced Packaging
Wafer BondingHybrid, eutectic, fusion Anodic BondingGlass to silicon, cavities MEMS Cap WafersCavities, ports, seal lands, bonded TSV FabricationHigh AR, void-free Cu fill InterposersSi and glass, TSV/TGV + RDL TSV RevealBackgrind → etch → CMP TGV FabricationThrough-glass via Glass TGV CouponsHole-only to routed prototypes RDL FabricationBCB / PBO / PI + damascene Packaging & AssemblyWire bond, flip-chip 3D / 2.5D PackagingTSV + RDL + UBM + C4 AuSn BumpPVD lift-off, fluxless Laser SubmountsSi/AlN submounts, optical benches Indium BumpEvap lift-off · cryo/quantum UBM DepositionTi/Pt/Au · adhesion-barrier-Au Cu Pillar & SnAg BumpingPillars with SnAg caps, SnAg bumps Gold BumpEvap & plated · Au-Au TC AuGe / AuSi356/363°C eutectic die attach High-Pb Bumps95Pb5Sn · hi-rel C4 SLID / TLPCu/Sn · Au/In · Ag/In Al-Ge Sealing424°C · CMOS-friendly MEMS Ohmic ContactsGaAs · GaN · RTA + TLM SiC ProcessingContacts, implant, 1800 °C anneal GaN & III-VGaN, GaAs, InP processing Cryo / UHV MetalAuSn · Ti/Pd/Au · rings Optical AccessWindows · meshes · holes Vapor CellsDRIE + bond · unfilled TFOI WafersQuartz-on-Si · LNOI Biochip & MicrofluidicsGlass 500×600 mm, NIL SiPho PackagingTSV · RDL · UBM · C4 for PIC
Industries
AI & HPC PackagingCoWoS-style, 2.5D / 3D Silicon PhotonicsSOI · AuSn · TSV interposer AutomotiveMEMS sensors, SiC power Life SciencesLab-on-chip, biosensors All Industries → Request a Quote →