Packaging test vehicles

Dummy Dies and
Daisy-Chain Test Chips

Silicon test dies that stand in for your product during assembly development: pad arrays at your pitch, daisy chains that close through the mating substrate, UBM and bumps of your choice, and probe pads to read every chain. Diced to size, identified, from one wafer.

Patterned test wafers →

Your pad pitchDaisy chains and KelvinUBM and bump optionsBare or bumpedDiced to sizeFrom 1 wafer
40 µm
Cu pillar pitch from,
reviewed geometries
Custom
Die size, subject to
layout and dicing review
4-8 in
Wafer
formats
1
Wafer minimum
order
What we build

Test dies that reveal the joint, not the device

Daisy-chain test structures measure continuity and total resistance through a defined group of assembled joints. Segmented chains help narrow the location of an open circuit; dedicated Kelvin structures can evaluate selected joints when the layout provides separate force and sense access. We fabricate the dies; assembly and electrical test are quoted separately or performed by you.

Test die (flipped)Bumps · Links on the dieLinks on the substrateChain terminals on the substrate

Schematic section of an assembled pair: die-side and substrate-side links alternate through the bumps, and the chain is read between the two terminals. Kelvin measurement of a selected joint needs separate force and sense routing.

01

Dummy dies

Mechanical stand-ins with pads, passivation and optional bumps, for pick-and-place, underfill and thermal trials without a live device.

02

Daisy-chain dies

Die-side links that close through the mating substrate to form the chain, with accessible start and end terminals. Segmentation narrows an open to a region; four-terminal Kelvin structures with separate force and sense routing are designed for selected joints where joint-level data are needed.

03

Bump and UBM options

Bare pads, UBM only, Cu pillar with SnAg cap, SnAg, AuSn or indium bumps, or Au bumps; solder routes delivered as-plated or reflowed, Au and indium as deposited. See Cu pillar and UBM.

04

Mating substrates

Matching interposer or substrate coupons with the complementary chain, so the pair closes the loop. See interposers.

At a glance

Dummy Dies and Daisy-Chain Test Chips

Scope and specification options. Every figure is confirmed for your program in the quotation.

40 µm
Cu pillar pitch from, reviewed geometries
Custom
Die size, subject to layout and dicing review
4-8 in
Wafer formats
1
Wafer minimum order
Your pad pitch
Daisy chains and Kelvin
UBM and bump options
Bare or bumped
Diced to size
From 1 wafer
Specification

Typical ranges

ParameterTypicalNote
Die sizeCustom, from about 1 × 1 mm up to the reticle field; larger by stitching where availableConfirmed after layout review; street width set to your saw or our dicing conditions
Pad and bump pitchCu pillar from 40 µm on reviewed geometries; solder bumps from about 80 µm; Au, AuSn and indium routes each have their own minimumPitch is confirmed per bump route and layout
Pad metalAl or Cu pads with polyimide or SiN passivationOpening size per pitch
Chain layoutSegmented chains, corner and edge chains, Kelvin structuresProbe pads at die edge or on the substrate
BumpsBare pads; UBM only; Cu pillar + SnAg cap; SnAg, AuSn or indium bumps; Au bumpsDelivery state by material: solder routes as-plated or reflowed, Au and indium as deposited or plated; height and diameter per pitch
ThicknessStandard or thinned to 100-200 µmThinning on carrier where needed
IdentificationDie ID marks and wafer mapTraceability per lot
InspectionOptical, bump height and coplanarity as agreedChain resistance is measured after assembly, a separate step; a dummy die is passive and is not a powered thermal test chip
How a program runs

From pitch to diced dies

Process flow
01Define the die02Layout03Fabricate04Inspect05Dice and deliver
  1. 01Define the dieSize, pitch, chain map, bump type, mating part.
  2. 02LayoutPad array and chain routing; GDS returned for approval.
  3. 03FabricateMetal, passivation, UBM and bumps per the option chosen.
  4. 04InspectOptical and bump metrology as agreed; wafer map.
  5. 05Dice and deliverDies to size in trays or on tape, identified.
What to send

For a test die quotation

ItemWhat helps
DieSize, thickness, quantity
ArrayPitch, bump count, chain netlist and segmentation, which joints need Kelvin access, viewing side and flip-chip mirror convention, test-pad access after assembly
BumpsType, height, delivery as-plated or reflowed
Mating partWhether you need matching substrates or already have them
ScheduleTarget date and stage of your assembly program
Direct answers

Questions engineers ask before ordering

What information is needed to quote a daisy-chain test die?

Die size and thickness, pad or bump pitch, bump count, chain segmentation and any Kelvin sites, bump type and delivery condition, whether you need matching substrates, quantity and date.

Do you also assemble and test the chains?

We fabricate the dies. Assembly and electrical test of the assembled chains are separate steps that can be quoted on request or kept in-house.

Can the dies be delivered without bumps?

Yes. Bare pads, UBM only, or bumped (Cu pillar with SnAg cap, SnAg, Au, AuSn, indium), as-plated or reflowed.

Related processes

Processes usually combined with this work

Patterned Test WafersCu Pillar & SnAgUBM DepositionInterposersDicing
Related service

Patterned Test Wafers: the process most often combined with this work, run in the same program.

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Start your project.
Initial response within one business day.

Share your process requirements, substrate, and production volume. A Nanosystems JP Inc. engineer gives an initial response, typically within one business day. A written quotation typically follows within 7-10 business days after we receive the required information and complete any prerequisite NDA.

To speed up technical review, please include:
substrate type & size  ·  target process  ·  quantity  ·  timeline  ·  design files if available (not required for first review)

sales@nanosystemsjp.co.jp · +81-3-5288-5569 · NDA available · All inquiries handled confidentially

Ready to discuss this process?
Initial engineering response typically within one business day. NDA available on request.
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Full process flow →
Substrates
Substrate & WafersSi, SiC, GaN, glass, sapphire Fused Silica WafersQuartz · borosilicate · low CTE PI Film & SUS Sensor FabRoll-to-roll · sensor patterning
Front-End
Mask FabricationGDS to chrome mask, DRC PhotolithographyE-beam 20nm to 500×600mm NanoimprintingUV & thermal NIL Thin Film DepositionPVD, CVD, ALD, MBE LiftoffMetal pattern · shadow mask ElectroplatingCu TSV fill, DPC, LIGA EtchingICP-RIE, DRIE >50:1 AnnealingN₂/H₂/vacuum/RTA Ion ImplantationB/P/As/Al/N implant CMP & GrindingCu CMP, 50µm thinning DicingBlade, stealth laser Wafer CleaningRCA, plasma, megasonic
Advanced Packaging
Wafer BondingHybrid, eutectic, fusion TSV FabricationHigh AR, void-free Cu fill TSV RevealBackgrind → etch → CMP TGV FabricationThrough-glass via RDL FabricationBCB/PBO/PI + damascene Packaging & AssemblyWire bond, flip-chip 📚 3D/2.5D PackagingTSV+RDL+UBM+C4 AuSn BumpPVD lift-off, fluxless Indium BumpEvap lift-off · cryo/quantum UBM DepositionTi/Pt/Au · adhesion-barrier-Au Gold BumpEvap & plated · Au-Au TC AuGe / AuSi356/363°C eutectic die attach High-Pb Bumps95Pb5Sn · hi-rel C4 SLID / TLPCu/Sn · Au/In · Ag/In Al-Ge Sealing424°C · CMOS-friendly MEMS Ohmic ContactsGaAs · GaN · RTA + TLM Cryo & UHV MetallizationAuSn · Ti/Pd/Au · seal rings Optical AccessWindows · meshes · thru-holes MEMS Vapor CellsDRIE + bond · unfilled bodies Thin-Film-on-InsulatorQuartz-on-Si · LNOI Biochip & MicrofluidicsGlass 500×600mm, NIL SiPho PackagingTSV·RDL·UBM·C4 for PIC
Industries
AI & HPC PackagingCoWoS-style, 2.5D/3D Silicon PhotonicsSOI · AuSn · TSV interposer Quantum TechnologyIon traps · vapor cells · TFOI AutomotiveMEMS sensors, SiC power Life SciencesLab-on-chip, biosensors All Industries → Request a Quote →
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Capabilities Overview
Substrates
Substrate & WafersSi, SiC, GaN, glass, sapphire Fused Silica WafersQuartz · borosilicate · low CTE Glass ProcessingDrilling, etching, polishing PI Film & SUS Sensor FabRoll-to-roll · sensor patterning
Front-End
Mask FabricationGDS to chrome mask, DRC PhotolithographyE-beam 20 nm to 500×600 mm NanoimprintingUV & thermal NIL Thin Film DepositionPVD, CVD, ALD, MBE ALD CoatingConformal oxides, nitrides PECVD DielectricsSiO₂, SiN, SiON, a-Si TFT & BackplaneIGZO · Glass · Display LiftoffMetal pattern · shadow mask ElectroplatingCu TSV fill, DPC, LIGA Electroforming & LIGANi shims, meshes, microstructures EtchingICP-RIE, DRIE >50:1 MEMS FoundrySensors, actuators, microfluidics Microchannel CoolingEtched, bonded, heater test chips Thermal Test ChipsHeater dies, multi-zone, RTD Temperature SensorsPt/NiCr RTDs, thermocouples AnnealingN₂ / H₂ / vacuum / RTA Ion ImplantationB / P / As / Al / N implant CMP & GrindingCu CMP, 50 µm thinning Wafer ThinningTo 50 µm on carriers Patterned Test WafersCustom CMP and process evaluation wafers Daisy-Chain Test DiesDummy dies, chains, bump options DicingBlade, stealth laser Wafer CleaningRCA, plasma, megasonic
Advanced Packaging
Wafer BondingHybrid, eutectic, fusion Anodic BondingGlass to silicon, cavities MEMS Cap WafersCavities, ports, seal lands, bonded TSV FabricationHigh AR, void-free Cu fill InterposersSi and glass, TSV/TGV + RDL TSV RevealBackgrind → etch → CMP TGV FabricationThrough-glass via Glass TGV CouponsHole-only to routed prototypes RDL FabricationBCB / PBO / PI + damascene Packaging & AssemblyWire bond, flip-chip 3D / 2.5D PackagingTSV + RDL + UBM + C4 AuSn BumpPVD lift-off, fluxless Laser SubmountsSi/AlN submounts, optical benches Indium BumpEvap lift-off · cryo/quantum UBM DepositionTi/Pt/Au · adhesion-barrier-Au Cu Pillar & SnAg BumpingPillars with SnAg caps, SnAg bumps Gold BumpEvap & plated · Au-Au TC AuGe / AuSi356/363°C eutectic die attach High-Pb Bumps95Pb5Sn · hi-rel C4 SLID / TLPCu/Sn · Au/In · Ag/In Al-Ge Sealing424°C · CMOS-friendly MEMS Ohmic ContactsGaAs · GaN · RTA + TLM SiC ProcessingContacts, implant, 1800 °C anneal GaN & III-VGaN, GaAs, InP processing Cryo / UHV MetalAuSn · Ti/Pd/Au · rings Optical AccessWindows · meshes · holes Vapor CellsDRIE + bond · unfilled TFOI WafersQuartz-on-Si · LNOI Biochip & MicrofluidicsGlass 500×600 mm, NIL SiPho PackagingTSV · RDL · UBM · C4 for PIC
Industries
AI & HPC PackagingCoWoS-style, 2.5D / 3D Silicon PhotonicsSOI · AuSn · TSV interposer AutomotiveMEMS sensors, SiC power Life SciencesLab-on-chip, biosensors All Industries → Request a Quote →