Wafer bonding

Anodic and
Glass-to-Silicon Bonding

Field-assisted bonding of borosilicate glass to silicon, and glass-silicon-glass stacks, for hermetic caps, microfluidic covers, pressure references and vapor cells. Cavities, electrical feedthroughs and alignment handled in the same program.

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Borosilicate to SiSi-glass-Si stacksHermetic cavitiesAligned bondingThrough-glass ports4-8 in
4-8 in
Wafer
diameters
300-450 °C
Typical bonding
temperature
±5 µm
Alignment,
typical
1
Wafer pair
minimum
What we bond

Glass to silicon, in the configurations MEMS needs

+Glass (borosilicate)SiliconCavity

Voltage and heat: conditions are set per material and structure.

🔬

Cap and cavity bonding

Etched or drilled glass over silicon structures, or silicon caps over glass, with sealed cavities at atmosphere or controlled pressure.

⚙️

Microfluidic covers

Glass lids over silicon channels with through-glass ports, or silicon over structured glass; fluidic sealing checked as agreed.

🧪

Triple stacks

Silicon-glass-silicon and glass-silicon-glass for vapor cells, optical windows and double-sided sensors. See vapor cells.

📐

Feedthroughs

Metal lines under the bond ring or through-silicon vias for electrical access to the sealed cavity; bond over topography reviewed per layout.

🧩

Aligned bonding

Front-to-front and front-to-back alignment to marks on both wafers, typically ±5 µm, tighter on request.

🔩

Alternatives

Where the thermal budget rules out anodic bonding, adhesive, low-temperature fusion or eutectic routes. See wafer bonding.

At a glance

Anodic and Glass-to-Silicon Bonding

Scope and specification options. Every figure is confirmed for your program in the quotation.

4-8 in
Wafer diameters
300-450 °C
Typical bonding temperature
±5 µm
Alignment, typical
1
Wafer pair minimum
Borosilicate to Si
Si-glass-Si stacks
Hermetic cavities
Aligned bonding
Through-glass ports
4-8 in
Capability

Typical ranges

ParameterTypicalNote
GlassBorosilicate matched to silicon expansion (Borofloat-type, Pyrex-type); alkali-free glass reviewedCustomer-supplied glass accepted after review
SiliconBare, oxidized (thin) or patterned; SOIBond over thin oxide reviewed
Temperature and voltage300-450 °C; voltage set per stackLower temperature with longer time on request
Alignment±5 µm typicalMarks on both wafers required
Cavity pressureAtmosphere, controlled gas, or reduced pressureGetter integration on inquiry
InspectionBond interface by IR imaging and optical inspection; hermeticity or leak test as agreedSacrificial dies for pull test on request
What to send

For a bonding quotation

ItemWhat helps
Both wafersMaterials, thicknesses, existing films and structures on each
Bond layoutBond ring width, cavity sizes, feedthrough routing
AlignmentMark positions and required accuracy
CavityRequired pressure or gas, hermeticity requirement
QuantityWafer pairs and target date
Related processes

Processes usually combined with this work

Wafer BondingMEMS FoundryMEMS Vapor CellsBiochip & MicrofluidicsGlass Wafer Processing
Related service

Wafer Bonding: the process most often combined with this work, run in the same program.

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Direct answers

Questions engineers ask before ordering

Can you use my glass?

Customer-supplied borosilicate is accepted after review; alkali-free glass is reviewed case by case.

What alignment accuracy?

±5 µm typical with marks on both wafers; tighter on request.

Can the cavity be sealed at reduced pressure?

Yes, atmosphere, controlled gas or reduced pressure; getter integration on inquiry.

Start your project.
Initial response within one business day.

Share your process requirements, substrate, and production volume. A Nanosystems JP Inc. engineer gives an initial response, typically within one business day. A written quotation typically follows within 7-10 business days after we receive the required information and complete any prerequisite NDA.

To speed up technical review, please include:
substrate type & size  ·  target process  ·  quantity  ·  timeline  ·  design files if available (not required for first review)

sales@nanosystemsjp.co.jp · +81-3-5288-5569 · NDA available · All inquiries handled confidentially

Ready to discuss this process?
Initial engineering response typically within one business day. NDA available on request.
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All Services
Full process flow →
Substrates
Substrate & WafersSi, SiC, GaN, glass, sapphire Fused Silica WafersQuartz · borosilicate · low CTE PI Film & SUS Sensor FabRoll-to-roll · sensor patterning
Front-End
Mask FabricationGDS to chrome mask, DRC PhotolithographyE-beam 20nm to 500×600mm NanoimprintingUV & thermal NIL Thin Film DepositionPVD, CVD, ALD, MBE LiftoffMetal pattern · shadow mask ElectroplatingCu TSV fill, DPC, LIGA EtchingICP-RIE, DRIE >50:1 AnnealingN₂/H₂/vacuum/RTA Ion ImplantationB/P/As/Al/N implant CMP & GrindingCu CMP, 50µm thinning DicingBlade, stealth laser Wafer CleaningRCA, plasma, megasonic
Advanced Packaging
Wafer BondingHybrid, eutectic, fusion TSV FabricationHigh AR, void-free Cu fill TSV RevealBackgrind → etch → CMP TGV FabricationThrough-glass via RDL FabricationBCB/PBO/PI + damascene Packaging & AssemblyWire bond, flip-chip 📚 3D/2.5D PackagingTSV+RDL+UBM+C4 AuSn BumpPVD lift-off, fluxless Indium BumpEvap lift-off · cryo/quantum UBM DepositionTi/Pt/Au · adhesion-barrier-Au Gold BumpEvap & plated · Au-Au TC AuGe / AuSi356/363°C eutectic die attach High-Pb Bumps95Pb5Sn · hi-rel C4 SLID / TLPCu/Sn · Au/In · Ag/In Al-Ge Sealing424°C · CMOS-friendly MEMS Ohmic ContactsGaAs · GaN · RTA + TLM Cryo & UHV MetallizationAuSn · Ti/Pd/Au · seal rings Optical AccessWindows · meshes · thru-holes MEMS Vapor CellsDRIE + bond · unfilled bodies Thin-Film-on-InsulatorQuartz-on-Si · LNOI Biochip & MicrofluidicsGlass 500×600mm, NIL SiPho PackagingTSV·RDL·UBM·C4 for PIC
Industries
AI & HPC PackagingCoWoS-style, 2.5D/3D Silicon PhotonicsSOI · AuSn · TSV interposer Quantum TechnologyIon traps · vapor cells · TFOI AutomotiveMEMS sensors, SiC power Life SciencesLab-on-chip, biosensors All Industries → Request a Quote →
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Capabilities Overview
Substrates
Substrate & WafersSi, SiC, GaN, glass, sapphire Fused Silica WafersQuartz · borosilicate · low CTE Glass ProcessingDrilling, etching, polishing PI Film & SUS Sensor FabRoll-to-roll · sensor patterning
Front-End
Mask FabricationGDS to chrome mask, DRC PhotolithographyE-beam 20 nm to 500×600 mm NanoimprintingUV & thermal NIL Thin Film DepositionPVD, CVD, ALD, MBE ALD CoatingConformal oxides, nitrides PECVD DielectricsSiO₂, SiN, SiON, a-Si TFT & BackplaneIGZO · Glass · Display LiftoffMetal pattern · shadow mask ElectroplatingCu TSV fill, DPC, LIGA Electroforming & LIGANi shims, meshes, microstructures EtchingICP-RIE, DRIE >50:1 MEMS FoundrySensors, actuators, microfluidics Microchannel CoolingEtched, bonded, heater test chips Thermal Test ChipsHeater dies, multi-zone, RTD Temperature SensorsPt/NiCr RTDs, thermocouples AnnealingN₂ / H₂ / vacuum / RTA Ion ImplantationB / P / As / Al / N implant CMP & GrindingCu CMP, 50 µm thinning Wafer ThinningTo 50 µm on carriers Patterned Test WafersCustom CMP and process evaluation wafers Daisy-Chain Test DiesDummy dies, chains, bump options DicingBlade, stealth laser Wafer CleaningRCA, plasma, megasonic
Advanced Packaging
Wafer BondingHybrid, eutectic, fusion Anodic BondingGlass to silicon, cavities MEMS Cap WafersCavities, ports, seal lands, bonded TSV FabricationHigh AR, void-free Cu fill InterposersSi and glass, TSV/TGV + RDL TSV RevealBackgrind → etch → CMP TGV FabricationThrough-glass via Glass TGV CouponsHole-only to routed prototypes RDL FabricationBCB / PBO / PI + damascene Packaging & AssemblyWire bond, flip-chip 3D / 2.5D PackagingTSV + RDL + UBM + C4 AuSn BumpPVD lift-off, fluxless Laser SubmountsSi/AlN submounts, optical benches Indium BumpEvap lift-off · cryo/quantum UBM DepositionTi/Pt/Au · adhesion-barrier-Au Cu Pillar & SnAg BumpingPillars with SnAg caps, SnAg bumps Gold BumpEvap & plated · Au-Au TC AuGe / AuSi356/363°C eutectic die attach High-Pb Bumps95Pb5Sn · hi-rel C4 SLID / TLPCu/Sn · Au/In · Ag/In Al-Ge Sealing424°C · CMOS-friendly MEMS Ohmic ContactsGaAs · GaN · RTA + TLM SiC ProcessingContacts, implant, 1800 °C anneal GaN & III-VGaN, GaAs, InP processing Cryo / UHV MetalAuSn · Ti/Pd/Au · rings Optical AccessWindows · meshes · holes Vapor CellsDRIE + bond · unfilled TFOI WafersQuartz-on-Si · LNOI Biochip & MicrofluidicsGlass 500×600 mm, NIL SiPho PackagingTSV · RDL · UBM · C4 for PIC
Industries
AI & HPC PackagingCoWoS-style, 2.5D / 3D Silicon PhotonicsSOI · AuSn · TSV interposer AutomotiveMEMS sensors, SiC power Life SciencesLab-on-chip, biosensors All Industries → Request a Quote →