GaN and III-V
Wafer Processing
Post-epitaxy processing for GaN, GaAs and InP devices: contacts, mesa and via etching, implantation, passivation, through-substrate vias on GaN-on-Si, bumping and dicing. From two-inch research pieces to eight-inch GaN-on-Si.
diameters
stack
etching
order
The steps between epitaxy and packaging
Ohmic and Schottky contacts
Ti/Al/Ni/Au and Ti/Al/Mo/Au on GaN; AuGe/Ni/Au on n-GaAs; Ti/Pt/Au and Pd-based on p-type; Ni/Au and Pt gates. Lift-off patterning and RTA alloying. See ohmic contacts.
Mesa, isolation and via etching
Cl₂/BCl₃ ICP-RIE for GaN and GaAs, CH₄/H₂ for InP; ion implantation isolation as an alternative to mesa etch. See etching.
Implantation and anneal
Isolation and doping implants; hydrogen depassivation of Mg-doped GaN at 700-1000 °C; implanted-Mg activation reviewed as a development topic. See ion implantation.
Passivation and dielectrics
PECVD SiN and ALD Al₂O₃ passivation and gate dielectrics; low-temperature routes for InP.
Through-substrate vias
TSV through GaN-on-Si for RF and power devices, backside metallization and RDL, slot vias where the layout needs them. See TSV.
Bumping, thinning and dicing
AuSn, gold or Cu pillar bumps for flip-chip; thinning on carriers; laser and blade dicing for brittle substrates.
GaN and III-V Wafer Processing
Scope and specification options. Every figure is confirmed for your program in the quotation.
By material
| Material | Typical work | Note |
|---|---|---|
| GaN-on-Si | Contacts, mesa etch, passivation, TSV, backside metal, RDL; 6 and 8 inch | Backside processing on carriers |
| GaN-on-SiC, GaN-on-sapphire | Contacts, etch, passivation, bumping; 2 to 4 inch | Sapphire backside on request |
| GaAs and AlGaAs | Mesa and trench etch to ~5 µm, ohmic contacts, backside metal; 2 to 4 inch | Al-containing layers etched by ICP-RIE |
| InP | Low-temperature contacts and passivation, mesa etch; 2 to 3 inch | Thermal budget agreed per stack |
| Contacts | Lift-off metal stacks, RTA to 1000 °C | Contact behaviour depends on doping, surface preparation and anneal |
For a III-V quotation
| Item | What helps |
|---|---|
| Epi structure | Layer stack with doping and thicknesses, or the data sheet that came with the wafers |
| Steps | Which steps, in order; which are already done |
| Contacts | Metal preference, target contact resistance, allowed anneal temperature |
| Etch | Depth, critical dimension, mask type, profile requirement |
| Quantity and stage | Pieces, wafers, target date |
Processes usually combined with this work
Questions engineers ask before ordering
Do you process GaAs and InP as well as GaN?
Yes. Mesa and trench etching, contacts and backside metal on GaAs and AlGaAs; low-temperature contacts and passivation on InP.
Can you make TSVs through GaN-on-Si?
Yes, including slot vias, backside metallization and RDL, with backside processing on carriers.
What do you need to quote?
Epi structure with doping and thicknesses, the step list in order, contact targets and allowed anneal temperature, etch depth and CD, quantity and date.
Start your project.
Initial response within one business day.
Share your process requirements, substrate, and production volume. A Nanosystems JP Inc. engineer gives an initial response, typically within one business day. A written quotation typically follows within 7-10 business days after we receive the required information and complete any prerequisite NDA.