SiC Wafer
Processing Services
The steps a silicon carbide device program needs after epitaxy: contact metallization, implantation and high-temperature activation, cleaning, thinning and dicing, on 4 to 8 inch 4H-SiC, from a few wafers.
diameters
anneal
metals
order
Process steps, each with its own review
SiC needs different chemistry, higher temperatures and harder mechanics than silicon. Each step below is quoted with those differences built in.
One example n-type ohmic stack on SiC, schematic. Schottky and p-type stacks differ; layers and thicknesses per program.
Ohmic and Schottky contacts, reviewed separately
Contact metallization is reviewed separately for ohmic and Schottky functions. The metal stack and thermal treatment depend on conductivity type, doping, surface preparation, existing films and the required electrical behavior: Ni and NiPt silicided by RTA for n-type ohmic contacts, Ti- and Al-based stacks for p-type, and unalloyed Schottky metals with their own barrier review. See ohmic contact metallization.
Ion implantation and activation
Al, N and P implants at room or elevated temperature, followed by activation anneal to 1800 °C with a carbon cap. Implant activation and contact annealing are separate process steps with independently defined conditions, and activation is scheduled before temperature-sensitive metal. Implant activation and contact annealing are separate process steps with independently defined conditions, and activation is scheduled before temperature-sensitive metal. See ion implantation and annealing.
Cleaning
RCA and SPM cleans on 4 to 8 inch SiC, including contamination-driven cleans before epitaxy or metallization. See wafer cleaning.
Thinning and dicing
Backgrinding to 100-200 µm on carriers, backside metallization, laser or blade dicing suited to the hardness of SiC.
Substrates
4H-SiC wafers sourced with your specification for orientation, doping and epi. See substrates.
Passivation and dielectrics
PECVD and thermal oxide films and field oxides as part of a device flow. Gate-dielectric work is quoted with its own interface characterization and electrical tests; offering oxidation does not by itself imply a qualified gate oxide.
SiC Wafer Processing Services
Scope and specification options. Every figure is confirmed for your program in the quotation.
Typical ranges on SiC
| Step | Typical capability | Note |
|---|---|---|
| Wafer size | 4, 6 and 8 inch 4H-SiC; pieces for feasibility | Supported diameter, wafer state and minimum lot are confirmed step by step (cleaning, implant, activation, metal, thinning, dicing), not assumed for every operation |
| Ohmic contacts | Ni, NiPt for n-type; Ti/Al-based for p-type; Ti/Ni/Au overlay; lift-off or subtractive metal etching | Specific contact resistance depends on doping, surface preparation and anneal; TLM or CTLM structures defined where contact data are required |
| Schottky contacts | Ti, Ni, Mo and other barrier metals, unalloyed or lightly annealed | Barrier height and ideality are device-level results agreed per program |
| Implant activation anneal | Up to 1800 °C in Ar with carbon cap; time and ramp per recipe | Requires a wafer state without temperature-sensitive metal |
| Contact anneal | Typically 900-1050 °C RTA in N₂ or Ar for ohmic alloying | Separate step with its own conditions |
| Implantation | Al, N, P; hot implant available | Species, energy and dose per your device |
| Cleaning | RCA, SPM, HF-based sequences | Particle and metallic contamination criteria agreed |
| Thinning | To 100-200 µm with carrier support | TTV and bow reported per lot |
For a SiC quotation
| Item | What helps |
|---|---|
| Wafer | Diameter, thickness, Si-face or C-face, off-axis angle, n- or p-type doping, epi thickness and doping, existing films or metals, carrier state, allowable backside damage |
| Step list | Which of the steps above, in what order, and what is already done |
| Contact targets | Metal preference, target specific contact resistance, allowed anneal temperature |
| Implant | Species, energy, dose, mask type, activation requirement |
| Quantity and stage | Feasibility pieces, prototype wafers, pilot; target date |
Processes usually combined with this work
Questions engineers ask before ordering
Can you process customer-supplied SiC wafers?
Yes, 4 to 8 inch 4H-SiC, and pieces for feasibility; sourced wafers are also available to your specification.
Do you offer the 1800 °C activation anneal?
Yes, with carbon cap, in N₂ or Ar, as part of an implant program or as a stand-alone step.
Which contact metals do you run on SiC?
For ohmic contacts, Ni and NiPt on n-type and Ti/Al-based stacks on p-type, silicided or alloyed by RTA; for Schottky contacts, unalloyed barrier metals reviewed per device. Contact resistance and barrier behaviour are agreed per doping, surface preparation and anneal.
Start your project.
Initial response within one business day.
Share your process requirements, substrate, and production volume. A Nanosystems JP Inc. engineer gives an initial response, typically within one business day. A written quotation typically follows within 7-10 business days after we receive the required information and complete any prerequisite NDA.