SiC Wafer
Processing Services
Thinning, metallization, implantation, annealing and dicing for 4H-SiC research, prototypes and pilot lots. Nanosystems JP Inc. supports individual process steps and multi-step programs on customer-supplied or sourced SiC wafers: wafer thinning, film deposition on one or both sides, ohmic and Schottky contact formation, ion implantation and activation, cleaning, and dicing. We confirm wafer size, existing layers, thermal limits and inspection requirements for each requested process.
12 in reviewed per program
typical minimum
in Ar, carbon cap
typical minimum
Nine SiC services, ordered singly or as one program
SiC calls for different chemistry, high-temperature treatments and specialized grinding and dicing processes compared with silicon. Each service below is quoted with those differences built in, on its own or combined with others, from one evaluation wafer to pilot lots on customer-supplied or sourced wafers.
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Modules are selected independently. The example sequence shows one device flow in which implant activation precedes temperature-sensitive metallization and thinning precedes dicing; the order for your program is fixed at the quotation.
Substrates
4H-SiC n-type and semi-insulating wafers in prime, production and dummy grades, 4, 6 and 8 inch, sourced to your orientation, off-angle, doping and epi specification; 12 inch n-type and dummy wafers on inquiry; pieces cut from larger wafers for feasibility. Availability by diameter, type and grade is confirmed at the quotation. See substrates.
Thinning (backgrind)
SiC wafer thinning with controlled grinding-side selection: material is removed from the C-face while the Si-face device surface is protected, or from the Si-face where the device sits on the C-face. Includes stress-relief polish, edge treatment, cleaning and a thickness map; carriers for thin wafers. Typical minimum 100 µm; thicknesses below 100 µm are subject to feasibility review. See wafer thinning.
Thin-film deposition
Metal films on one or both sides, with a different stack per side where needed: Ti, Ni, Cu, Al, Mo, Cr, Nb, Ta, Pt, Au and Ag by sputtering (10 nm to 2 µm per layer) or e-beam evaporation (10 nm to 1 µm per layer, lift-off compatible); thicker Cu, Ni or Au by electroplating; PECVD oxide and nitride 50 nm to 5 µm per film; LPCVD polysilicon and polyimide per specification. Ranges by material and method are in the table below. See wafer metallization and backside metallization.
Ohmic and Schottky contacts, reviewed separately
Contact metallization is reviewed separately for ohmic and Schottky functions. The stack and thermal treatment follow conductivity type, doping, surface preparation, existing films and the required electrical behavior: Ni alloyed by RTA for n-type ohmic contacts (a Ni-Pt alloy by co-sputtering as a calibration program), Ti- and Al-based stacks for p-type, and unalloyed Schottky metals with their own barrier review. TLM or CTLM structures are patterned alongside where contact data are required. See ohmic contact metallization.
Ion implantation and activation
Al, N and P implants at room or elevated temperature (to 600 °C), followed by activation annealing at 1400 to 1800 °C in Ar under a carbon cap, with conditions selected for the implant and the wafer structure. Implant activation and contact annealing are separate process steps with independently defined conditions; activation is scheduled before temperature-sensitive metal. See ion implantation and annealing.
Cleaning
RCA (SC1, SC2), SPM and HF-based sequences, selected for the contamination to be removed and the films already on the wafer; incoming cleans before epitaxy or metallization and post-implant cleans. The sequence and its compatibility with existing layers are stated in the quotation. See wafer cleaning.
Dicing to chips
Blade or laser dicing into square chips from about 3 × 3 mm, rectangular formats such as 10 × 20 mm, and several sizes from one wafer; MOSFET and diode chips, test coupons. Chip dimensions, street width, kerf and dimensional tolerance are specified separately in the quotation. Delivered on the dicing frame, in trays or in chip carriers. See dicing.
Laser cutting and marking
Custom outlines, circular or irregular pieces and downsizing, for example 6 inch wafers into 2 or 4 inch pieces, by laser with low kerf loss; laser marking of face identification or IDs. Confirmed per material and thickness. See stealth and laser dicing.
Passivation and dielectrics
PECVD oxide and nitride films and field oxides as part of a device flow; thermal oxidation of SiC is reviewed per program. Gate-dielectric work is quoted with its own interface characterization and electrical tests; offering oxidation does not by itself imply a qualified gate oxide.
Limits by process
SiC parameters depend on wafer diameter, thickness, doping and surface condition; the quotation states the values for your wafers.
Wafer diameter by process
| Process | 4 in | 6 in | 8 in | 12 in |
|---|---|---|---|---|
| Substrate supply (4H-SiC) | Standard | Standard | Standard | Per program (n-type, dummy) |
| Thinning | Standard | Standard | Standard | Per program |
| Thin films: sputtering, e-beam, PECVD | Standard | Standard | Standard | Per program |
| Electroplating | Standard | Standard | Standard | Per program |
| Contact metallization and RTA | Standard | Standard | Standard | Per program |
| Ion implantation | Standard | Standard | Standard | Per program |
| Activation anneal to 1800 °C | Standard | Standard | Per program | Per program |
| Thermal oxidation | Standard | Standard | Per program | Per program |
| Cleaning | Standard | Standard | Standard | Per program |
| Dicing and laser cutting | Standard | Standard | Standard | Per program |
Standard: quoted from the published ranges. Per program: confirmed for the specific wafer and process before the quotation. Pieces and 2 inch wafers on inquiry.
Typical ranges and acceptance
| Parameter | Typical | Acceptance and notes |
|---|---|---|
| Substrates | n-type and semi-insulating 4H-SiC; prime, production and dummy; Si-face or C-face polished; epi per specification | Substrate CoC supplied with sourced wafers; for customer-supplied wafers, incoming data as provided |
| Thinning | To 100 µm typical minimum; grind face Si or C; stress-relief polish, edge treatment | Mean thickness ±5 µm typical after grinding, ±3 µm with polish; TTV, bow and warp limits agreed per program; below 100 µm subject to feasibility review |
| Sputtered metals | Ti, Ni, Cu, Al, Mo, Cr, Nb, Ta, Pt, Au, Ag; 10 nm to 2 µm per layer; one or both sides | Thickness on a witness coupon from the same run; on-wafer uniformity map on request |
| E-beam evaporated metals | Ti, Ni, Pt, Au, Al; 10 nm to 1 µm per layer; lift-off patterning | Same measurement options; lift-off registration per the ohmic contact page |
| Electroplated metals | Cu, Ni, Au where microns are needed; thickness per specification | Reviewed per program |
| PECVD dielectrics | SiO₂, SiN, SiON; 50 nm to 5 µm per film; 150 to 400 °C | Thickness and refractive index by ellipsometry on request |
| Thermal oxide, gate dielectric | Thermal oxidation of SiC reviewed per program | Interface characterization and electrical tests quoted separately; not a qualified gate oxide by default |
| Polysilicon and polyimide | LPCVD poly-Si; polyimide, cure per grade | Thickness per specification |
| Ohmic contacts | Ni for n-type (Ni-Pt alloy by co-sputtering as a calibration program); Ti/Al-based for p-type; Ti/Ni/Au or Au overlay; lift-off or subtractive etching | Specific contact resistivity ρc (Ω·cm²) from TLM or CTLM structures on request; depends on doping, surface preparation and anneal |
| Schottky contacts | Ti, Ni, Mo and other barrier metals, unalloyed or lightly annealed | Target barrier height, ideality factor and measurement conditions are agreed for each device |
| Implantation | Al, N, P; room temperature or hot implant to 600 °C; oxide or resist mask per energy | Dose and energy per profile; sheet resistance after activation on request |
| Activation anneal | 1400 to 1800 °C in Ar under a carbon cap; time and ramp per recipe; cap removal included | Activation confirmed per lot by sheet resistance or Hall measurement on request |
| Contact anneal | Typically 900 to 1050 °C RTA, N₂ or Ar per recipe | Separate step from activation |
| Cleaning | RCA (SC1, SC2), SPM, HF-based | Sequence selected for the contamination and the existing films; stated in the quotation |
| Dicing | Square chips from about 3 × 3 mm; rectangular formats; several sizes per wafer; blade or laser | Chip dimensions, street width, kerf and dimensional tolerance specified separately; edge-chipping criteria agreed per lot |
| Laser cutting and marking | Custom outlines, circular pieces, downsizing, marking | Confirmed per material and thickness |
| Delivery | Whole wafers in single-wafer cases or cassettes; chips on frame, in trays or carriers | Inspection report per lot; substrate CoC where available |
Thinning plus backside metallization
A typical backside program on a finished device wafer: grinding from the C-face while the Si-face device surface is protected, stress-relief polish, edge treatment and cleaning, then a thickness map. Where the backside carries current, a Ni-based backside ohmic contact is formed and annealed first, with conditions chosen for the thinned wafer and the front-side thermal budget; the Ti/Ni/Ag or Ti/Ni/Au finish for die attach follows. Thin wafers travel on carriers or in single-wafer cases.
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Schematic, not to scale; starting and final thickness, grind face, contact structure and finish stack are set per program.
Contact interface and thermal order
The ohmic contact and the finish metal are separate layers with separate purposes. Ni deposited on n-type SiC and alloyed by RTA forms the electrical interface; the Au or Al overlay on the front, or the Ti/Ni/Ag finish on the back, carries the current to the wire, clip or solder. The order follows the thermal budget: implant and activation first, contact RTA next, then overlays and finishes, so that no temperature-sensitive metal sees the activation anneal.
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One example n-type ohmic stack on SiC, schematic. Schottky and p-type stacks differ; layers and thicknesses per program.
Metallized test coupons plus dicing
A common SiC order is a metal stack on a whole wafer, diced into chips and shipped ready to use: Ti/Ni/Au or Ti/Pt/Au on 3 × 3 mm or 5 × 5 mm chips, Ni contact patterns, or backside Ti/Ni/Ag on thinned die. Film thickness is measured on a witness coupon from the same deposition run and reported with the lot; this records the deposited thickness and does not by itself establish uniformity across the wafer, so an on-wafer thickness map, XRR or cross-section SEM are quoted separately where required. Chips are supplied on dicing frames for subsequent die handling and assembly, or sorted in trays and chip carriers.
Swipe horizontally to view the full diagram.
Schematic; chip sizes, outlines and delivery format are fixed at the quotation.
What is measured, and what is optional
| Item | Included with the lot | On request |
|---|---|---|
| Thickness after thinning | Mean thickness and thickness map | TTV, bow and warp report |
| Film thickness | Witness coupon from the same deposition run | On-wafer thickness map, XRR, cross-section SEM |
| Film properties | Visual inspection | Sheet resistance, stress, refractive index, tape adhesion test |
| Contacts | Process record of stack and anneal | ρc from TLM or CTLM structures; I-V on Schottky structures |
| Implant and activation | Dose and energy record | Sheet resistance, Hall measurement, SIMS |
| Chips | Visual inspection and count per size | AOI for edge chipping; dimensional check against agreed criteria |
| Documents | Inspection report per lot; substrate CoC for sourced wafers where available | Customer-specific report formats |
Delivery: whole wafers in single-wafer cases or cassettes, thin wafers on carriers, chips on dicing frames or sorted in trays and chip carriers.
Where SiC processing is ordered
Power MOSFET and diode prototypes
Contact, implant, anneal, thinning and backside metal modules for vertical device programs after epitaxy.
Schottky and JBS diodes
Unalloyed barrier metals with their own review, edge termination implants, backside ohmic contact.
RF on semi-insulating SiC
Semi-insulating 4H-SiC substrates and metallization for RF and microwave test structures.
High-temperature sensors and MEMS
Thin-film deposition, contact formation and dicing on SiC for sensors that run where silicon cannot.
Metallized test chips and coupons
Ti/Ni/Au, Ti/Pt/Au or Ni patterns on SiC diced to 3 to 10 mm chips for bonding, die-attach and materials tests.
University and research lots
Single wafers or pieces with a written process record; documented process conditions support repeat orders.
For a SiC quotation
| Item | What helps |
|---|---|
| Wafer | Diameter, thickness, Si-face or C-face, off-axis angle, n- or p-type doping, epi thickness and doping, existing films or metals, carrier state, allowable backside damage |
| Step list | Which of the services above, in what order, and what is already done |
| Films | Side (front, back or both), stack and thickness per side, method preference, thickness acceptance and measurement |
| Contact targets | Metal preference, target specific contact resistivity, allowed anneal temperature |
| Implant | Species, energy, dose, mask type, activation requirement |
| Thinning and chips | Final thickness and grind face; chip sizes, orientation to the flat, quantity per size, delivery on frame, tray or carrier |
| Acceptance | Thickness tolerance, TTV, bow, film uniformity, chip dimensions and chipping limits; which measurements must be included |
| Quantity and stage | Feasibility pieces, prototype wafers, pilot; target date |
Processes usually combined with this work
Questions engineers ask before ordering
Which SiC wafer diameters do you process?
4, 6 and 8 inch 4H-SiC as standard for thinning, thin films, contacts, implantation, cleaning and dicing. 12 inch wafers are reviewed per program, with n-type and dummy grades available for sourcing. Activation annealing to 1800 °C on 8 and 12 inch wafers is reviewed per program. Pieces are accepted for feasibility.
How thin can SiC be ground, and from which face?
To 100 µm as a typical minimum; thicknesses below 100 µm are subject to feasibility review. The grind face is chosen per device: from the C-face while the Si-face device surface is protected, or from the Si-face where the device sits on the C-face.
Can you deposit different films on the two sides?
Yes. Each side can carry its own stack and thickness, for example a Ni contact pattern on the front and Ti/Ni/Ag on the back, scheduled around the anneal steps.
Do you offer the 1800 °C activation anneal?
Yes: 1400 to 1800 °C in Ar under a carbon cap, with time, ramp and cap removal set for the implant and the wafer structure, as part of an implant program or as a stand-alone step.
Which contact metals do you run on SiC?
For n-type ohmic contacts, Ni alloyed by RTA; a Ni-Pt alloy deposited by co-sputtering is offered as a calibration program. For p-type, Ti- and Al-based stacks. For Schottky contacts, unalloyed barrier metals reviewed per device. Specific contact resistivity and barrier behavior are measured on TLM, CTLM or diode structures on request and depend on doping, surface preparation and anneal.
How are chips delivered?
On dicing frames for subsequent die handling and assembly, or sorted in trays or chip carriers. Square chips from about 3 × 3 mm, rectangular formats and several sizes from one wafer, with dimensions and tolerances fixed at the quotation.
Request a SiC processing quote.
Initial response typically within one business day.
Share your process requirements, substrate, and production volume. A Nanosystems JP Inc. engineer gives an initial response, typically within one business day. A written quotation typically follows within 7-10 business days after we receive the required information and complete any prerequisite NDA.