PECVD Dielectrics
SiO₂, SiN, SiON, SiCN and a-Si
Plasma-enhanced CVD films at temperatures a finished device tolerates: passivation, interlayer dielectric, hard masks, low-stress nitride for membranes, index-tuned oxynitride for photonics, silicon carbonitride (SiCN) as a low-k barrier and etch stop, and hydrogenated amorphous silicon. Stress, index and thickness are set for your stack.
temperature
range, typical
refractive index
capability
What we deposit and why
Schematic dielectric stack; each film specified by thickness, stress and index.
Silicon oxide
Silane or TEOS oxide for interlayer dielectric, hard masks, liners and CMP stop layers; thicker oxides where thermal oxidation is not possible.
Silicon nitride
Passivation and moisture barrier; low-stress nitride for membranes, cantilevers and released structures; etch masks for KOH and DRIE.
Oxynitride
Refractive index tuned between oxide and nitride for waveguide cladding, AR layers and stress balancing.
Silicon carbonitride (SiCN)
Low-k dielectric barrier and etch-stop films, including thin SiCN over metal layers such as Ru, TiN or Cu where a capping layer must combine low permittivity with diffusion resistance; composition and density tuned by process, thickness from tens of nanometers.
Amorphous silicon
a-Si and a-Si:H for sacrificial layers, TFT channels, photoconductors and hard masks, with hydrogen content controlled by process.
Stress engineering
Compressive to tensile films, and balanced front and back stacks, to control wafer bow after deposition.
Low-temperature routes
Films at 150 to 200 °C for polymer, III-V and completed CMOS surfaces.
PECVD Dielectrics SiO₂, SiN, SiON and a-Si
Scope and specification options. Every figure is confirmed for your program in the quotation.
Typical ranges
Values are typical process windows; the quotation states the specification for your film.
| Parameter | Typical | Note |
|---|---|---|
| Films | SiO₂ (silane, TEOS), SiN, SiON, SiCN, a-Si, a-Si:H, SiC | DLC and doped oxides on inquiry |
| Thickness | 50 nm to 5 µm per film; SiCN capping layers from about 20 nm | Thicker by multiple depositions |
| Temperature | 150 to 400 °C | Selected for the thermal budget |
| Stress | Tunable from compressive to tensile; low-stress nitride available | Measured by wafer bow per lot |
| Refractive index | SiON tunable between ~1.46 and ~2.0 | Ellipsometry on request |
| Formats | Pieces, wafers to 300 mm, panels to 500 × 600 mm | Panel films confirmed per program |
For a PECVD quotation
| Item | What helps |
|---|---|
| Film | Material, thickness and tolerance, stress target, index target |
| Substrate | Material, size, existing films and topography |
| Thermal budget | Maximum temperature allowed |
| Downstream | What the film must survive: etch, CMP, bonding, reflow |
| Quantity | Pieces, wafers or panels and target date |
Processes usually combined with this work
Questions engineers ask before ordering
Can you tune film stress?
Yes, from compressive to tensile, including low-stress nitride for membranes; stress is measured by wafer bow per lot.
What is the lowest deposition temperature?
150 °C routes are available for polymer, III-V and completed CMOS surfaces.
Do you coat panels?
Yes, panels to 500 × 600 mm, confirmed per program.
Start your project.
Initial response typically within one business day.
Share your process requirements, substrate, and production volume. A Nanosystems JP Inc. engineer gives an initial response, typically within one business day. A written quotation typically follows within 7-10 business days after we receive the required information and complete any prerequisite NDA.