Thermal test vehicles

Custom Thermal Test Chips
and Thin-Film Microheaters

Custom resistive heater chips designed to reproduce an agreed heated footprint and power distribution for cooling and package evaluation. We review resistance, supply limits, operating temperature and the thermal interface together; inspection and temperature-characterization scope are defined in the quotation. For qualifying cold plates, thermal interface materials, lids and packages, delivered as diced chips or on the wafer.

Microchannel cooling structures →

Single or multi-zone heatersNiCr, Pt, TiW heatersTarget resistanceOn-chip RTD optionSi, glass, AlN substratesFrom 1 wafer
1-100 W
Power class
per chip, typical
1 mm-25 mm
Heated area
edge length
±5%
Resistance tolerance
typical, ±2% on request
1
Wafer minimum
order
What we build

A heater die designed around your measurement

Cooling and interface tests are only as good as the heat source. We design the heater to your heated area, power density and zone map, and put the contacts and sensors where your fixture needs them.

Zone 1 heater · Zone 2 heaterDrive pads (+/-)RTD sense padsIsolation, substrate, TIM, cold plate

Schematic: two independently driven zones with drive and return pads, a separate RTD sense line, and the thermal stack below. Heated zones, resistance and pad layout are designed per specification.

01

Single-zone heaters

One serpentine element sized to your footprint and resistance, with wide pads for wire, ribbon or spring-probe contact.

02

Multi-zone and hotspot chips

Independently driven zones to reproduce hotspots and non-uniform power maps, with shared or separate returns.

03

Integrated temperature sensing

Two distinct options: a local thin-film RTD element on the chip, or four-wire measurement of the heater resistance, which gives a calibrated effective heater temperature rather than a hotspot map. Characterization scope is agreed in advance. See temperature sensors.

04

Delivery formats

Diced chips to your die size, chips on carrier, or full wafers; backside metallized or bare for your interface material.

At a glance

Custom Thermal Test Chips and Thin-Film Microheaters

Scope and specification options. Every figure is confirmed for your program in the quotation.

1-100 W
Power class per chip, typical
1 mm-25 mm
Heated area edge length
±5%
Resistance tolerance typical, ±2% on request
1
Wafer minimum order
Single or multi-zone heaters
NiCr, Pt, TiW heaters
Target resistance
On-chip RTD option
Si, glass, AlN substrates
From 1 wafer
Specification

Typical ranges

The values below are typical process windows; the quotation states the specification for your chip.

ParameterTypicalNote
SubstrateSilicon 200-725 µm with oxide or nitride isolation under the heater; glass; AlN for high heat fluxHeater-to-substrate isolation and breakdown requirement stated per program; customer-supplied substrates reviewed
Heater metalNiCr, Pt, TiW, W; Au or Al contact overlayChosen for resistance, stability and temperature
Resistance0.5 Ω to several kΩ per zone, chosen with the power and supply limitsResistance, voltage and current are reviewed together (100 W into 0.5 Ω is 14 A, which sets the film, trace and pad design); tolerance ±5% typical at a stated reference temperature, ±2% with laser or design trim
Heated area1 × 1 mm to 25 × 25 mm; larger on inquiryZone count and layout per design
Power1 W to 100 W class per chipDepends on substrate, die thickness, backside finish, interface material, mounting pressure and cooling; continuous versus pulsed operation, duty cycle and maximum heater temperature are set per program and confirmed by test where agreed
ContactsAu pads for wire bond or probe; solderable pads on requestPad size and placement per fixture
PassivationPECVD SiO₂ or SiN; ALD Al₂O₃ where a thin barrier is neededOptional, per environment
InspectionResistance of every zone on every chip, measured on the wafer before dicing at a stated reference temperature; optical inspectionReport per lot as standard, per die on request; thermal mapping and burn-in are separate agreed items
How a program runs

From footprint to tested chips

Process flow
01Define the heater02Layout03Fabrication04Test05Dice and deliver
  1. 01Define the heaterHeated area, zones, power, resistance, pad positions, sensor needs.
  2. 02LayoutMeander geometry and film thickness set to the resistance target; GDS returned for approval.
  3. 03FabricationMetal deposition and lift-off or subtractive metal etching, passivation, pad overlay.
  4. 04TestResistance of every zone on every chip before dicing; burn-in and thermal mapping as separately agreed items.
  5. 05Dice and deliverChips to size with identification, or wafers with a map.
What to send

For a heater quotation

ItemWhat helps
FootprintChip size, heated area and zone layout, or the device it should mimic
ElectricalTarget resistance or supply voltage and current limit per zone; number of independent zones; DC or pulsed operation and duty cycle; target heater temperature
InterfaceBackside finish, bare or metallized; interface material, cooling arrangement and mounting pressure you will use
SensingLocal RTD, thermocouple, or four-wire heater resistance; required characterization range, points and report content
QuantityChips or wafers, delivery format, target date
Direct answers

Questions engineers ask before ordering

Can you deliver diced heater chips?

Yes. Chips are diced to your die size and identified, or delivered on the wafer with a map. Backside can be bare or metallized for your interface material.

What do you need to quote a heater die?

Chip size, heated area and zone layout, target resistance or supply voltage and power, pad positions, sensing needs, quantity and date. A sketch is enough; drawings can follow.

Can you add a temperature sensor on the same chip?

Yes. A thin-film RTD line or four-wire heater sensing can be fabricated on the same chip; calibration scope is agreed before fabrication.

Related processes

Processes usually combined with this work

Microchannel CoolingTemperature SensorsWafer MetallizationPECVD DielectricsDicing
Related service

Microchannel Cooling: the process most often combined with this work, run in the same program.

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Start your project.
Initial response within one business day.

Share your process requirements, substrate, and production volume. A Nanosystems JP Inc. engineer gives an initial response, typically within one business day. A written quotation typically follows within 7-10 business days after we receive the required information and complete any prerequisite NDA.

To speed up technical review, please include:
substrate type & size  ·  target process  ·  quantity  ·  timeline  ·  design files if available (not required for first review)

sales@nanosystemsjp.co.jp · +81-3-5288-5569 · NDA available · All inquiries handled confidentially

Ready to discuss this process?
Initial engineering response typically within one business day. NDA available on request.
Request a Quote →
All Services
Full process flow →
Substrates
Substrate & WafersSi, SiC, GaN, glass, sapphire Fused Silica WafersQuartz · borosilicate · low CTE PI Film & SUS Sensor FabRoll-to-roll · sensor patterning
Front-End
Mask FabricationGDS to chrome mask, DRC PhotolithographyE-beam 20nm to 500×600mm NanoimprintingUV & thermal NIL Thin Film DepositionPVD, CVD, ALD, MBE LiftoffMetal pattern · shadow mask ElectroplatingCu TSV fill, DPC, LIGA EtchingICP-RIE, DRIE >50:1 AnnealingN₂/H₂/vacuum/RTA Ion ImplantationB/P/As/Al/N implant CMP & GrindingCu CMP, 50µm thinning DicingBlade, stealth laser Wafer CleaningRCA, plasma, megasonic
Advanced Packaging
Wafer BondingHybrid, eutectic, fusion TSV FabricationHigh AR, void-free Cu fill TSV RevealBackgrind → etch → CMP TGV FabricationThrough-glass via RDL FabricationBCB/PBO/PI + damascene Packaging & AssemblyWire bond, flip-chip 📚 3D/2.5D PackagingTSV+RDL+UBM+C4 AuSn BumpPVD lift-off, fluxless Indium BumpEvap lift-off · cryo/quantum UBM DepositionTi/Pt/Au · adhesion-barrier-Au Gold BumpEvap & plated · Au-Au TC AuGe / AuSi356/363°C eutectic die attach High-Pb Bumps95Pb5Sn · hi-rel C4 SLID / TLPCu/Sn · Au/In · Ag/In Al-Ge Sealing424°C · CMOS-friendly MEMS Ohmic ContactsGaAs · GaN · RTA + TLM Cryo & UHV MetallizationAuSn · Ti/Pd/Au · seal rings Optical AccessWindows · meshes · thru-holes MEMS Vapor CellsDRIE + bond · unfilled bodies Thin-Film-on-InsulatorQuartz-on-Si · LNOI Biochip & MicrofluidicsGlass 500×600mm, NIL SiPho PackagingTSV·RDL·UBM·C4 for PIC
Industries
AI & HPC PackagingCoWoS-style, 2.5D/3D Silicon PhotonicsSOI · AuSn · TSV interposer Quantum TechnologyIon traps · vapor cells · TFOI AutomotiveMEMS sensors, SiC power Life SciencesLab-on-chip, biosensors All Industries → Request a Quote →
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Capabilities Overview
Substrates
Substrate & WafersSi, SiC, GaN, glass, sapphire Fused Silica WafersQuartz · borosilicate · low CTE Glass ProcessingDrilling, etching, polishing PI Film & SUS Sensor FabRoll-to-roll · sensor patterning
Front-End
Mask FabricationGDS to chrome mask, DRC PhotolithographyE-beam 20 nm to 500×600 mm NanoimprintingUV & thermal NIL Thin Film DepositionPVD, CVD, ALD, MBE ALD CoatingConformal oxides, nitrides PECVD DielectricsSiO₂, SiN, SiON, a-Si TFT & BackplaneIGZO · Glass · Display LiftoffMetal pattern · shadow mask ElectroplatingCu TSV fill, DPC, LIGA Electroforming & LIGANi shims, meshes, microstructures EtchingICP-RIE, DRIE >50:1 MEMS FoundrySensors, actuators, microfluidics Microchannel CoolingEtched, bonded, heater test chips Thermal Test ChipsHeater dies, multi-zone, RTD Temperature SensorsPt/NiCr RTDs, thermocouples AnnealingN₂ / H₂ / vacuum / RTA Ion ImplantationB / P / As / Al / N implant CMP & GrindingCu CMP, 50 µm thinning Wafer ThinningTo 50 µm on carriers Patterned Test WafersCustom CMP and process evaluation wafers Daisy-Chain Test DiesDummy dies, chains, bump options DicingBlade, stealth laser Wafer CleaningRCA, plasma, megasonic
Advanced Packaging
Wafer BondingHybrid, eutectic, fusion Anodic BondingGlass to silicon, cavities MEMS Cap WafersCavities, ports, seal lands, bonded TSV FabricationHigh AR, void-free Cu fill InterposersSi and glass, TSV/TGV + RDL TSV RevealBackgrind → etch → CMP TGV FabricationThrough-glass via Glass TGV CouponsHole-only to routed prototypes RDL FabricationBCB / PBO / PI + damascene Packaging & AssemblyWire bond, flip-chip 3D / 2.5D PackagingTSV + RDL + UBM + C4 AuSn BumpPVD lift-off, fluxless Laser SubmountsSi/AlN submounts, optical benches Indium BumpEvap lift-off · cryo/quantum UBM DepositionTi/Pt/Au · adhesion-barrier-Au Cu Pillar & SnAg BumpingPillars with SnAg caps, SnAg bumps Gold BumpEvap & plated · Au-Au TC AuGe / AuSi356/363°C eutectic die attach High-Pb Bumps95Pb5Sn · hi-rel C4 SLID / TLPCu/Sn · Au/In · Ag/In Al-Ge Sealing424°C · CMOS-friendly MEMS Ohmic ContactsGaAs · GaN · RTA + TLM SiC ProcessingContacts, implant, 1800 °C anneal GaN & III-VGaN, GaAs, InP processing Cryo / UHV MetalAuSn · Ti/Pd/Au · rings Optical AccessWindows · meshes · holes Vapor CellsDRIE + bond · unfilled TFOI WafersQuartz-on-Si · LNOI Biochip & MicrofluidicsGlass 500×600 mm, NIL SiPho PackagingTSV · RDL · UBM · C4 for PIC
Industries
AI & HPC PackagingCoWoS-style, 2.5D / 3D Silicon PhotonicsSOI · AuSn · TSV interposer AutomotiveMEMS sensors, SiC power Life SciencesLab-on-chip, biosensors All Industries → Request a Quote →