Thin-film sensors

Thin-Film Temperature
Sensor Fabrication

Platinum thin-film RTDs and custom thermocouple structures fabricated to your substrate and layout: silicon, glass, ceramic or polyimide film. Nominal resistance, operating range, temperature coefficient, electrical screening and any temperature calibration are specified separately for the selected film stack.

Thermal test chips →Temperature Sensors

Pt and NiCr RTDsThin-film thermocouplesSi, glass, AlN, polyimideLift-off patternedPassivated contactsFrom 1 substrate
Pt100 / Pt1000
Nominal resistance
options
20 µm
Line width
from
By stack
Operating range, set by
film, substrate and contacts
1
Substrate minimum
order
What we build

Sensors where you need them, not where a package allows

Pt meander (RTD) with 4 terminalsPassivation over the elementsThermocouple: junction and 2 terminalsSubstrate

Schematic: RTD terminals for four-wire measurement, a thermocouple with its two lead terminals (reference junction handled at the readout), and the passivation tint over the elements. Geometry and metal system follow the substrate and temperature range.

01

Platinum RTDs

Meander elements with a nominal 100 Ω or 1000 Ω at 0 °C, annealed for a stable temperature coefficient; on silicon, glass and AlN. The measured coefficient, tolerance and range are reported for the stack, not implied from the name.

02

NiCr and alloy resistors for sensing

NiCr and similar films are primarily heater and resistor materials; some grades have a very low temperature coefficient. They can be characterized for embedded sensing or heater feedback on the same chip, with the alloy, film and measured sensitivity stated per program.

03

Thin-film thermocouples

Dissimilar-metal junctions (Sb/Bi, Cu/constantan-type, Pt/Pt-Rh) patterned by lift-off, including arrays on polyimide for surface mapping; each pair has its own fabrication and temperature review, and a NiCr/Ni pair is a custom pair unless its alloys and response match a recognized type. Reference-junction treatment and readout are agreed with the layout. See the flexible substrate page.

04

Integration

Passivation, contact overlays, solderable pads and dicing; sensors integrated into heater chips, microchannel structures or your own device flow.

At a glance

Thin-Film Temperature Sensor Fabrication

Scope and specification options. Every figure is confirmed for your program in the quotation.

Pt100 / Pt1000
Nominal resistance options
20 µm
Line width from
By stack
Operating range, set by film, substrate and contacts
1
Substrate minimum order
Pt and NiCr RTDs
Thin-film thermocouples
Si, glass, AlN, polyimide
Lift-off patterned
Passivated contacts
From 1 substrate
Specification

Typical ranges

Sensor performance depends on substrate, film and anneal; the quotation states what is measured and how.

ParameterTypicalNote
Substrates and rangeSi with oxide, glass, fused silica, AlN, polyimide filmThe usable temperature range is set by the whole stack: substrate, adhesion and passivation, contacts, atmosphere and exposure time; polyimide builds are limited by the film, not the metal
RTD metalsPt (sputtered or evaporated), NiCr, NiAdhesion layer per substrate
Thermocouple pairsSb/Bi, Cu/constantan-type, Pt/Pt-Rh; NiCr/Ni as a custom pairSeebeck response characterized by agreement; reference-junction treatment, lead and pad materials stated per design
Line width20 µm and up by lift-off; finer on requestMeander design per resistance
Film thickness100 nm to 1 µmSet for resistance and stability
Nominal resistance100 Ω or 1000 Ω at 0 °C, or customTemperature coefficient, tolerance and trimming reported per program; two-, three- or four-wire configuration and excitation current agreed for the readout
PassivationSiO₂, SiN or Al₂O₃; polyimide on flexible partsOptional
Electrical screeningResistance measured on every element at a stated reference temperatureEstablishes the electrical value at that condition, not a temperature-response curve
Temperature characterization or calibrationAvailable by agreement: R(T) over the agreed range, number of points, reference method, uncertainty, drift and hysteresis checks as specifiedReporting scope defined in advance in the quotation
How a program runs

From drawing to characterized sensors

Process flow
01Define the sensor02Layout03Fabricate04Screen andcharacterize05Deliver
  1. 01Define the sensorType, range, resistance, substrate, contact layout.
  2. 02LayoutElement and pad geometry; GDS returned for approval.
  3. 03FabricateDeposition and lift-off, anneal, passivation, contacts.
  4. 04Screen and characterizeResistance of every element at a stated reference temperature; temperature characterization where agreed.
  5. 05DeliverDiced or on wafer, with data and identification.
What to send

For a sensor quotation

ItemWhat helps
SensorRTD or thermocouple, target resistance or pair, operating range
SubstrateMaterial, size, whether you supply it
LayoutElement positions, pad positions, connection method
EnvironmentChemical exposure, cycling, passivation needs
CharacterizationRequired range, number of points, reference method and report content; RTD wiring (two-, three- or four-wire) and thermocouple reference-junction arrangement
Direct answers

Questions engineers ask before ordering

Do you calibrate the sensors?

Every element is screened electrically at a stated reference temperature. Temperature characterization or calibration is quoted separately, with points, reference method and reporting scope defined in advance.

Can you fabricate sensors on my own substrate?

Yes, on silicon, glass, fused silica, AlN or polyimide film after a review of the surface and thermal budget.

Which sensor type should I choose?

Platinum RTDs for stable, well-characterized resistance thermometry; NiCr-type resistors only where a characterized embedded element is acceptable; thin-film thermocouples where a junction measurement or an array is needed.

Related service

Thermal Test Chips: the process most often combined with this work, run in the same program.

View page →

Start your project.
Initial response within one business day.

Share your process requirements, substrate, and production volume. A Nanosystems JP Inc. engineer gives an initial response, typically within one business day. A written quotation typically follows within 7-10 business days after we receive the required information and complete any prerequisite NDA.

To speed up technical review, please include:
substrate type & size  ·  target process  ·  quantity  ·  timeline  ·  design files if available (not required for first review)

sales@nanosystemsjp.co.jp · +81-3-5288-5569 · NDA available · All inquiries handled confidentially

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Initial engineering response typically within one business day. NDA available on request.
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Substrates
Substrate & WafersSi, SiC, GaN, glass, sapphire Fused Silica WafersQuartz · borosilicate · low CTE PI Film & SUS Sensor FabRoll-to-roll · sensor patterning
Front-End
Mask FabricationGDS to chrome mask, DRC PhotolithographyE-beam 20nm to 500×600mm NanoimprintingUV & thermal NIL Thin Film DepositionPVD, CVD, ALD, MBE LiftoffMetal pattern · shadow mask ElectroplatingCu TSV fill, DPC, LIGA EtchingICP-RIE, DRIE >50:1 AnnealingN₂/H₂/vacuum/RTA Ion ImplantationB/P/As/Al/N implant CMP & GrindingCu CMP, 50µm thinning DicingBlade, stealth laser Wafer CleaningRCA, plasma, megasonic
Advanced Packaging
Wafer BondingHybrid, eutectic, fusion TSV FabricationHigh AR, void-free Cu fill TSV RevealBackgrind → etch → CMP TGV FabricationThrough-glass via RDL FabricationBCB/PBO/PI + damascene Packaging & AssemblyWire bond, flip-chip 📚 3D/2.5D PackagingTSV+RDL+UBM+C4 AuSn BumpPVD lift-off, fluxless Indium BumpEvap lift-off · cryo/quantum UBM DepositionTi/Pt/Au · adhesion-barrier-Au Gold BumpEvap & plated · Au-Au TC AuGe / AuSi356/363°C eutectic die attach High-Pb Bumps95Pb5Sn · hi-rel C4 SLID / TLPCu/Sn · Au/In · Ag/In Al-Ge Sealing424°C · CMOS-friendly MEMS Ohmic ContactsGaAs · GaN · RTA + TLM Cryo & UHV MetallizationAuSn · Ti/Pd/Au · seal rings Optical AccessWindows · meshes · thru-holes MEMS Vapor CellsDRIE + bond · unfilled bodies Thin-Film-on-InsulatorQuartz-on-Si · LNOI Biochip & MicrofluidicsGlass 500×600mm, NIL SiPho PackagingTSV·RDL·UBM·C4 for PIC
Industries
AI & HPC PackagingCoWoS-style, 2.5D/3D Silicon PhotonicsSOI · AuSn · TSV interposer Quantum TechnologyIon traps · vapor cells · TFOI AutomotiveMEMS sensors, SiC power Life SciencesLab-on-chip, biosensors All Industries → Request a Quote →
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Capabilities Overview
Substrates
Substrate & WafersSi, SiC, GaN, glass, sapphire Fused Silica WafersQuartz · borosilicate · low CTE Glass ProcessingDrilling, etching, polishing PI Film & SUS Sensor FabRoll-to-roll · sensor patterning
Front-End
Mask FabricationGDS to chrome mask, DRC PhotolithographyE-beam 20 nm to 500×600 mm NanoimprintingUV & thermal NIL Thin Film DepositionPVD, CVD, ALD, MBE ALD CoatingConformal oxides, nitrides PECVD DielectricsSiO₂, SiN, SiON, a-Si TFT & BackplaneIGZO · Glass · Display LiftoffMetal pattern · shadow mask ElectroplatingCu TSV fill, DPC, LIGA Electroforming & LIGANi shims, meshes, microstructures EtchingICP-RIE, DRIE >50:1 MEMS FoundrySensors, actuators, microfluidics Microchannel CoolingEtched, bonded, heater test chips Thermal Test ChipsHeater dies, multi-zone, RTD Temperature SensorsPt/NiCr RTDs, thermocouples AnnealingN₂ / H₂ / vacuum / RTA Ion ImplantationB / P / As / Al / N implant CMP & GrindingCu CMP, 50 µm thinning Wafer ThinningTo 50 µm on carriers Patterned Test WafersCustom CMP and process evaluation wafers Daisy-Chain Test DiesDummy dies, chains, bump options DicingBlade, stealth laser Wafer CleaningRCA, plasma, megasonic
Advanced Packaging
Wafer BondingHybrid, eutectic, fusion Anodic BondingGlass to silicon, cavities MEMS Cap WafersCavities, ports, seal lands, bonded TSV FabricationHigh AR, void-free Cu fill InterposersSi and glass, TSV/TGV + RDL TSV RevealBackgrind → etch → CMP TGV FabricationThrough-glass via Glass TGV CouponsHole-only to routed prototypes RDL FabricationBCB / PBO / PI + damascene Packaging & AssemblyWire bond, flip-chip 3D / 2.5D PackagingTSV + RDL + UBM + C4 AuSn BumpPVD lift-off, fluxless Laser SubmountsSi/AlN submounts, optical benches Indium BumpEvap lift-off · cryo/quantum UBM DepositionTi/Pt/Au · adhesion-barrier-Au Cu Pillar & SnAg BumpingPillars with SnAg caps, SnAg bumps Gold BumpEvap & plated · Au-Au TC AuGe / AuSi356/363°C eutectic die attach High-Pb Bumps95Pb5Sn · hi-rel C4 SLID / TLPCu/Sn · Au/In · Ag/In Al-Ge Sealing424°C · CMOS-friendly MEMS Ohmic ContactsGaAs · GaN · RTA + TLM SiC ProcessingContacts, implant, 1800 °C anneal GaN & III-VGaN, GaAs, InP processing Cryo / UHV MetalAuSn · Ti/Pd/Au · rings Optical AccessWindows · meshes · holes Vapor CellsDRIE + bond · unfilled TFOI WafersQuartz-on-Si · LNOI Biochip & MicrofluidicsGlass 500×600 mm, NIL SiPho PackagingTSV · RDL · UBM · C4 for PIC
Industries
AI & HPC PackagingCoWoS-style, 2.5D / 3D Silicon PhotonicsSOI · AuSn · TSV interposer AutomotiveMEMS sensors, SiC power Life SciencesLab-on-chip, biosensors All Industries → Request a Quote →