MEMS

MEMS Foundry
and Prototyping Services

Sensor, actuator, microfluidic and photonic MEMS built from one wafer upward: deep etching, wafer bonding, thin films, lithography, release and dicing, each step managed end to end by a dedicated project manager. Bring a drawing or a process flow; we return a feasibility answer and a route.

How ordering works →

DRIE and releaseWafer bondingThin filmsSOI and glassFrom 1 waferPrototype to pilot
1
Wafer minimum
order
2-12 in
Wafer
diameters
>50:1
DRIE
aspect ratio
1 day
Initial response
target
What we build

The process building blocks, in one program

A MEMS device rarely needs one process. It needs six in the right order, with the interfaces between them controlled. That coordination is what we sell.

01Substrate02Lithography03Deep etch04Thin films05Bonding06Release and diceA representative MEMS flow; the order and the steps are set by your device.
🔬

Inertial and pressure sensors

DRIE springs, proof masses and membranes on SOI or bulk silicon; cavities and backside etch to a buried oxide; hermetic caps by eutectic, anodic or glass-frit bonding.

⚙️

Microfluidics and biochips

Channels and reservoirs in silicon, glass or quartz; through-holes for ports; bonded covers and patterned electrodes. See biochip and microfluidics.

🧪

Optical MEMS and photonics

Mirrors, gratings, V-grooves and alignment features; metallized reflectors; benches and submounts for hybrid integration.

📐

Actuators and resonators

Piezoelectric (AlN, PZT) and electrostatic structures with patterned electrodes, release etching and controlled stress films.

🧩

Vapor cells and packages

Alkali vapor cells and hermetic MEMS packages by multi-wafer bonding; see MEMS vapor cells.

🔩

Test structures

Trench ladders, membrane arrays and bond-strength coupons that let you qualify a step before a full build. See test wafers.

At a glance

MEMS Foundry and Prototyping Services

Scope and specification options. Every figure is confirmed for your program in the quotation.

1
Wafer minimum order
2-12 in
Wafer diameters
>50:1
DRIE aspect ratio
1 day
Initial response target
DRIE and release
Wafer bonding
Thin films
SOI and glass
From 1 wafer
Prototype to pilot
Capability

What is typical, and what is reviewed

The table gives the ranges we quote routinely. Anything outside it is reviewed at engineering review before a quotation.

ElementTypical capabilityNote
SubstratesSi, SOI, glass, fused silica, quartz, sapphire; 2 to 12 inchCustomer-supplied or sourced by us
Deep silicon etchBosch DRIE, aspect ratio above 50:1 on narrow features, through-waferSee deep silicon etching
LithographyContact, stepper and e-beam; multi-layer overlayMask sets made to our 150 mm template or yours
Thin filmsSputtering, evaporation, PECVD, LPCVD, ALD; piezoelectric AlN and PZTSee the material library
BondingAnodic, fusion, eutectic (AuSn, AuSi, Al-Ge), adhesive, SLIDCavity and vacuum sealing reviewed per design
Release and dicingHF vapor and wet release, critical point drying, blade and stealth dicingFragile-structure handling agreed in advance
How a MEMS program runs

From drawing to diced devices

Process flow
01Feasibility review02Process definition03Masks and testcoupons04Fabrication05Release, dicing andinspection06Repeat lots
  1. 01Feasibility reviewWe read your device drawing or flow, check each step against the ranges above and list open questions, typically within one business day.
  2. 02Process definitionA step-by-step flow with inspection points, mask layout requirements and the substrate specification.
  3. 03Masks and test couponsMask set fabrication; where a step is new for the design, a short coupon run before committing wafers.
  4. 04FabricationLithography, etching, deposition and bonding run in the agreed order with metrology at the agreed points.
  5. 05Release, dicing and inspectionStructure release, singulation and the inspection deliverables in the quotation (optical, SEM, profilometry, electrical as agreed).
  6. 06Repeat lotsThe flow is kept on file; later lots need only quantity, date and any change note.
What to send

For a feasibility answer

ItemWhat helps
Device drawing or process flowCross-section sketch with layer thicknesses; GDS if you have it; which dimensions are critical
SubstrateMaterial, diameter, thickness, SOI device and BOX thickness, who supplies it
Critical stepsThe one or two steps you consider risky (deep etch depth, bond hermeticity, release stiction)
Quantity and stageFeasibility coupons, prototype wafers, pilot lot; target date
ConstraintsMaximum process temperature, restricted materials, existing devices on the wafer
Direct answers

Questions engineers ask before ordering

What is the minimum order?

One wafer. Feasibility coupons are also possible when a single step needs proving first.

Can you run my existing process flow?

Yes. Send the flow with layer thicknesses and critical dimensions; we check each step against our ranges and return the open questions within one business day.

Do you make the masks?

Yes, on our 150 mm template or to your mask specification.

Related processes

Processes usually combined with this work

Deep Silicon EtchingWafer BondingThin Film DepositionPhotolithographyDicingTest Wafers
Related service

Deep Silicon Etching: the process most often combined with this work, run in the same program.

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Start your project.
Initial response within one business day.

Share your process requirements, substrate, and production volume. A Nanosystems JP Inc. engineer gives an initial response, typically within one business day. A written quotation typically follows within 7-10 business days after we receive the required information and complete any prerequisite NDA.

To speed up technical review, please include:
substrate type & size  ·  target process  ·  quantity  ·  timeline  ·  design files if available (not required for first review)

sales@nanosystemsjp.co.jp · +81-3-5288-5569 · NDA available · All inquiries handled confidentially

Ready to discuss this process?
Initial engineering response typically within one business day. NDA available on request.
Request a Quote →
All Services
Full process flow →
Substrates
Substrate & WafersSi, SiC, GaN, glass, sapphire Fused Silica WafersQuartz · borosilicate · low CTE PI Film & SUS Sensor FabRoll-to-roll · sensor patterning
Front-End
Mask FabricationGDS to chrome mask, DRC PhotolithographyE-beam 20nm to 500×600mm NanoimprintingUV & thermal NIL Thin Film DepositionPVD, CVD, ALD, MBE LiftoffMetal pattern · shadow mask ElectroplatingCu TSV fill, DPC, LIGA EtchingICP-RIE, DRIE >50:1 AnnealingN₂/H₂/vacuum/RTA Ion ImplantationB/P/As/Al/N implant CMP & GrindingCu CMP, 50µm thinning DicingBlade, stealth laser Wafer CleaningRCA, plasma, megasonic
Advanced Packaging
Wafer BondingHybrid, eutectic, fusion TSV FabricationHigh AR, void-free Cu fill TSV RevealBackgrind → etch → CMP TGV FabricationThrough-glass via RDL FabricationBCB/PBO/PI + damascene Packaging & AssemblyWire bond, flip-chip 📚 3D/2.5D PackagingTSV+RDL+UBM+C4 AuSn BumpPVD lift-off, fluxless Indium BumpEvap lift-off · cryo/quantum UBM DepositionTi/Pt/Au · adhesion-barrier-Au Gold BumpEvap & plated · Au-Au TC AuGe / AuSi356/363°C eutectic die attach High-Pb Bumps95Pb5Sn · hi-rel C4 SLID / TLPCu/Sn · Au/In · Ag/In Al-Ge Sealing424°C · CMOS-friendly MEMS Ohmic ContactsGaAs · GaN · RTA + TLM Cryo & UHV MetallizationAuSn · Ti/Pd/Au · seal rings Optical AccessWindows · meshes · thru-holes MEMS Vapor CellsDRIE + bond · unfilled bodies Thin-Film-on-InsulatorQuartz-on-Si · LNOI Biochip & MicrofluidicsGlass 500×600mm, NIL SiPho PackagingTSV·RDL·UBM·C4 for PIC
Industries
AI & HPC PackagingCoWoS-style, 2.5D/3D Silicon PhotonicsSOI · AuSn · TSV interposer Quantum TechnologyIon traps · vapor cells · TFOI AutomotiveMEMS sensors, SiC power Life SciencesLab-on-chip, biosensors All Industries → Request a Quote →
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Capabilities Overview
Substrates
Substrate & WafersSi, SiC, GaN, glass, sapphire Fused Silica WafersQuartz · borosilicate · low CTE Glass ProcessingDrilling, etching, polishing PI Film & SUS Sensor FabRoll-to-roll · sensor patterning
Front-End
Mask FabricationGDS to chrome mask, DRC PhotolithographyE-beam 20 nm to 500×600 mm NanoimprintingUV & thermal NIL Thin Film DepositionPVD, CVD, ALD, MBE ALD CoatingConformal oxides, nitrides PECVD DielectricsSiO₂, SiN, SiON, a-Si TFT & BackplaneIGZO · Glass · Display LiftoffMetal pattern · shadow mask ElectroplatingCu TSV fill, DPC, LIGA Electroforming & LIGANi shims, meshes, microstructures EtchingICP-RIE, DRIE >50:1 MEMS FoundrySensors, actuators, microfluidics Microchannel CoolingEtched, bonded, heater test chips Thermal Test ChipsHeater dies, multi-zone, RTD Temperature SensorsPt/NiCr RTDs, thermocouples AnnealingN₂ / H₂ / vacuum / RTA Ion ImplantationB / P / As / Al / N implant CMP & GrindingCu CMP, 50 µm thinning Wafer ThinningTo 50 µm on carriers Patterned Test WafersCustom CMP and process evaluation wafers Daisy-Chain Test DiesDummy dies, chains, bump options DicingBlade, stealth laser Wafer CleaningRCA, plasma, megasonic
Advanced Packaging
Wafer BondingHybrid, eutectic, fusion Anodic BondingGlass to silicon, cavities MEMS Cap WafersCavities, ports, seal lands, bonded TSV FabricationHigh AR, void-free Cu fill InterposersSi and glass, TSV/TGV + RDL TSV RevealBackgrind → etch → CMP TGV FabricationThrough-glass via Glass TGV CouponsHole-only to routed prototypes RDL FabricationBCB / PBO / PI + damascene Packaging & AssemblyWire bond, flip-chip 3D / 2.5D PackagingTSV + RDL + UBM + C4 AuSn BumpPVD lift-off, fluxless Laser SubmountsSi/AlN submounts, optical benches Indium BumpEvap lift-off · cryo/quantum UBM DepositionTi/Pt/Au · adhesion-barrier-Au Cu Pillar & SnAg BumpingPillars with SnAg caps, SnAg bumps Gold BumpEvap & plated · Au-Au TC AuGe / AuSi356/363°C eutectic die attach High-Pb Bumps95Pb5Sn · hi-rel C4 SLID / TLPCu/Sn · Au/In · Ag/In Al-Ge Sealing424°C · CMOS-friendly MEMS Ohmic ContactsGaAs · GaN · RTA + TLM SiC ProcessingContacts, implant, 1800 °C anneal GaN & III-VGaN, GaAs, InP processing Cryo / UHV MetalAuSn · Ti/Pd/Au · rings Optical AccessWindows · meshes · holes Vapor CellsDRIE + bond · unfilled TFOI WafersQuartz-on-Si · LNOI Biochip & MicrofluidicsGlass 500×600 mm, NIL SiPho PackagingTSV · RDL · UBM · C4 for PIC
Industries
AI & HPC PackagingCoWoS-style, 2.5D / 3D Silicon PhotonicsSOI · AuSn · TSV interposer AutomotiveMEMS sensors, SiC power Life SciencesLab-on-chip, biosensors All Industries → Request a Quote →