Dry etching

ICP-RIE
Etching Services

Inductively coupled plasma reactive ion etching where the profile, selectivity and surface matter: waveguides and gratings, mesas and trenches in III-V and GaN, oxide and nitride hard masks and windows, SiC and quartz structures. Chemistry and bias are set for your material and mask, from a few pieces to 200 mm wafers.

All etching methods →

Si, SiO₂, SiNGaN, GaAs, InPSiC, quartz, glassFluorine and chlorine chemistriesAnisotropic profiles2-8 in
2-8 in
Wafer
diameters
Sub-100 nm
Feature size with
e-beam masks
>10:1
Selectivity to mask
typical, material dependent
1
Wafer or piece
minimum order
What we etch

ICP-RIE, and why it differs from RIE and wet etching

ICP-RIE controls plasma density and ion energy separately, so a high etch rate can be combined with low damage and a chosen profile. Wet etching is isotropic or crystal-plane bound; parallel-plate RIE couples rate to ion energy. ICP-RIE is the tool for vertical sidewalls, smooth surfaces and selectivity in materials that resist wet chemistry.

Mask · ICP-RIE: near-vertical sidewallIsotropic (wet or plasma) for comparisonSubstrate

Schematic, not to scale: an ICP-RIE trench with near-vertical sidewalls under a hard mask, beside an isotropic profile for comparison. Sidewall angle and roughness are measured on a cross section per program.

🔬

Silicon and SOI

Fluorine-based ICP-RIE for waveguides, gratings, shallow trenches and mesas in silicon and SOI; Bosch DRIE for deep structures is on its own page.

⚙️

Oxide and nitride

Fluorocarbon chemistries for SiO₂, SiN and SiON windows, hard masks, spacers and cladding etch-back with controlled selectivity to silicon and resist.

🧪

GaN, AlGaN, GaAs, InP

Chlorine and methane-hydrogen chemistries for mesa isolation, via and recess etching with low damage to the active layers.

📐

SiC

Fluorine ICP-RIE for trenches, mesas and vias in 4H-SiC with metal or oxide hard masks; rates and selectivity per depth.

🧩

Quartz, fused silica and glass

Fluorine chemistries for optical and MEMS structures in quartz and fused silica; profile and roughness reviewed against the optical requirement.

🔩

Metals and hard masks

Cr, Ni, Al and Ti masks and their removal; mask choice reviewed with the etch depth and selectivity.

At a glance

ICP-RIE Etching Services

Scope and specification options. Every figure is confirmed for your program in the quotation.

2-8 in
Wafer diameters
Sub-100 nm
Feature size with e-beam masks
>10:1
Selectivity to mask typical, material dependent
1
Wafer or piece minimum order
Si, SiO₂, SiN
GaN, GaAs, InP
SiC, quartz, glass
Fluorine and chlorine chemistries
Anisotropic profiles
2-8 in
Capability

Typical ranges

Etch results depend on material, mask, pattern density and depth; the quotation states what is measured and how.

ParameterTypicalNote
MaterialsSi, SOI, poly-Si, SiO₂, SiN, SiON, GaN, AlGaN, GaAs, AlGaAs, InP, SiC, quartz, fused silica, glassOthers reviewed
ChemistriesSF₆, C₄F₈, CHF₃, CF₄, Cl₂, BCl₃, CH₄/H₂, O₂, ArSelected per material and mask
DepthTens of nm to tens of µm; deep silicon by Bosch DRIERate and uniformity per recipe
ProfileNear-vertical to controlled taper; sidewall angle measuredNotching and trenching reviewed
Feature sizeSub-100 nm with e-beam lithography; contact and stepper for larger featuresMask on our 150 mm template or yours
SelectivityAbove 10:1 to typical hard masks, material dependentStated per program
FormatsPieces, 2 to 8 inch wafersLarger by inquiry
How a program runs

From pattern to measured profile

Process flow
01Define02Recipe03Etch04Measure05Deliver
  1. 01DefineMaterial, film stack, depth, CD, profile, mask type, downstream steps.
  2. 02RecipeChemistry, pressure, ICP and bias power chosen; coupon run for new combinations.
  3. 03EtchLithography and mask, ICP-RIE, mask strip and clean.
  4. 04MeasureProfilometry, cross-section SEM, CD and roughness as agreed.
  5. 05DeliverWafers or pieces with the measurement data.
Direct answers

Questions engineers ask before ordering

ICP-RIE or DRIE?

ICP-RIE for features up to tens of micrometers where profile, smoothness and selectivity matter; Bosch DRIE for deep silicon at high aspect ratio. Both are quoted together when a device needs both.

Can you etch III-V wafers without damaging the active layers?

Low-bias chlorine or methane-hydrogen recipes are used for GaN and InP mesas and recesses; damage-sensitive steps are reviewed with the epi structure.

What do you need to quote?

Material and film stack, etch depth and critical dimension, profile requirement, mask preference or whether we should pattern, quantity and date.

Related processes

Processes usually combined with this work

EtchingDeep Silicon EtchingGaN & III-VSiC ProcessingPhotonic Devices
Related service

Etching: the process most often combined with this work, run in the same program.

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Start your project.
Initial response within one business day.

Share your process requirements, substrate, and production volume. A Nanosystems JP Inc. engineer gives an initial response, typically within one business day. A written quotation typically follows within 7-10 business days after we receive the required information and complete any prerequisite NDA.

To speed up technical review, please include:
substrate type & size  ·  target process  ·  quantity  ·  timeline  ·  design files if available (not required for first review)

sales@nanosystemsjp.co.jp · +81-3-5288-5569 · NDA available · All inquiries handled confidentially

Ready to discuss this process?
Initial engineering response typically within one business day. NDA available on request.
Request a Quote →
All Services
Full process flow →
Substrates
Substrate & WafersSi, SiC, GaN, glass, sapphire Fused Silica WafersQuartz · borosilicate · low CTE PI Film & SUS Sensor FabRoll-to-roll · sensor patterning
Front-End
Mask FabricationGDS to chrome mask, DRC PhotolithographyE-beam 20nm to 500×600mm NanoimprintingUV & thermal NIL Thin Film DepositionPVD, CVD, ALD, MBE LiftoffMetal pattern · shadow mask ElectroplatingCu TSV fill, DPC, LIGA EtchingICP-RIE, DRIE >50:1 AnnealingN₂/H₂/vacuum/RTA Ion ImplantationB/P/As/Al/N implant CMP & GrindingCu CMP, 50µm thinning DicingBlade, stealth laser Wafer CleaningRCA, plasma, megasonic
Advanced Packaging
Wafer BondingHybrid, eutectic, fusion TSV FabricationHigh AR, void-free Cu fill TSV RevealBackgrind → etch → CMP TGV FabricationThrough-glass via RDL FabricationBCB/PBO/PI + damascene Packaging & AssemblyWire bond, flip-chip 📚 3D/2.5D PackagingTSV+RDL+UBM+C4 AuSn BumpPVD lift-off, fluxless Indium BumpEvap lift-off · cryo/quantum UBM DepositionTi/Pt/Au · adhesion-barrier-Au Gold BumpEvap & plated · Au-Au TC AuGe / AuSi356/363°C eutectic die attach High-Pb Bumps95Pb5Sn · hi-rel C4 SLID / TLPCu/Sn · Au/In · Ag/In Al-Ge Sealing424°C · CMOS-friendly MEMS Ohmic ContactsGaAs · GaN · RTA + TLM Cryo & UHV MetallizationAuSn · Ti/Pd/Au · seal rings Optical AccessWindows · meshes · thru-holes MEMS Vapor CellsDRIE + bond · unfilled bodies Thin-Film-on-InsulatorQuartz-on-Si · LNOI Biochip & MicrofluidicsGlass 500×600mm, NIL SiPho PackagingTSV·RDL·UBM·C4 for PIC
Industries
AI & HPC PackagingCoWoS-style, 2.5D/3D Silicon PhotonicsSOI · AuSn · TSV interposer Quantum TechnologyIon traps · vapor cells · TFOI AutomotiveMEMS sensors, SiC power Life SciencesLab-on-chip, biosensors All Industries → Request a Quote →
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Capabilities Overview
Substrates
Substrate & WafersSi, SiC, GaN, glass, sapphire Fused Silica WafersQuartz · borosilicate · low CTE Glass ProcessingDrilling, etching, polishing PI Film & SUS Sensor FabRoll-to-roll · sensor patterning
Front-End
Mask FabricationGDS to chrome mask, DRC PhotolithographyE-beam 20 nm to 500×600 mm NanoimprintingUV & thermal NIL Thin Film DepositionPVD, CVD, ALD, MBE ALD CoatingConformal oxides, nitrides PECVD DielectricsSiO₂, SiN, SiON, a-Si TFT & BackplaneIGZO · Glass · Display LiftoffMetal pattern · shadow mask ElectroplatingCu TSV fill, DPC, LIGA Electroforming & LIGANi shims, meshes, microstructures EtchingICP-RIE, DRIE >50:1 ICP-RIE EtchingSi, oxide, III-V, SiC, quartz MEMS FoundrySensors, actuators, microfluidics Microchannel CoolingEtched, bonded, heater test chips Thermal Test ChipsHeater dies, multi-zone, RTD Temperature SensorsPt/NiCr RTDs, thermocouples AnnealingN₂ / H₂ / vacuum / RTA Ion ImplantationB / P / As / Al / N implant CMP & GrindingCu CMP, 50 µm thinning Wafer ThinningTo 50 µm on carriers Patterned Test WafersCustom CMP and process evaluation wafers Daisy-Chain Test DiesDummy dies, chains, bump options DicingBlade, stealth laser Stealth & Laser Dicing300 mm Si and glass, SDBG Wafer CleaningRCA, plasma, megasonic Cleaning ChemistryPiranha, SC-1, SC-2, RCA
Advanced Packaging
Wafer BondingHybrid, eutectic, fusion Anodic BondingGlass to silicon, cavities MEMS Cap WafersCavities, ports, seal lands, bonded TSV FabricationHigh AR, void-free Cu fill InterposersSi and glass, TSV/TGV + RDL TSV RevealBackgrind → etch → CMP TGV FabricationThrough-glass via Glass TGV CouponsHole-only to routed prototypes RDL FabricationBCB / PBO / PI + damascene Packaging & AssemblyWire bond, flip-chip Flip-Chip BondingTC, reflow, AuSn, underfill 3D / 2.5D PackagingTSV + RDL + UBM + C4 AuSn BumpPVD lift-off, fluxless Laser SubmountsSi/AlN submounts, optical benches Indium BumpEvap lift-off · cryo/quantum UBM DepositionTi/Pt/Au · adhesion-barrier-Au Cu Pillar & SnAg BumpingPillars with SnAg caps, SnAg bumps Gold BumpEvap & plated · Au-Au TC AuGe / AuSi356/363°C eutectic die attach High-Pb Bumps95Pb5Sn · hi-rel C4 SLID / TLPCu/Sn · Au/In · Ag/In Al-Ge Sealing424°C · CMOS-friendly MEMS Ohmic ContactsGaAs · GaN · RTA + TLM SiC ProcessingContacts, implant, 1800 °C anneal GaN & III-VGaN, GaAs, InP processing Cryo / UHV MetalAuSn · Ti/Pd/Au · rings Optical AccessWindows · meshes · holes Vapor CellsDRIE + bond · unfilled TFOI WafersQuartz-on-Si · LNOI Biochip & MicrofluidicsGlass 500×600 mm, NIL SiPho PackagingTSV · RDL · UBM · C4 for PIC Photonic DevicesSiN/SOI waveguides, gratings
Industries
AI & HPC PackagingCoWoS-style, 2.5D / 3D Silicon PhotonicsSOI · AuSn · TSV interposer AutomotiveMEMS sensors, SiC power Life SciencesLab-on-chip, biosensors All Industries → Request a Quote →