Wafer cleaning

Piranha, SC-1, SC-2
and RCA Cleaning Services

The standard wet cleans, run as a service on your wafers: piranha for organics and resist residue, SC-1 for particles, SC-2 for metallic contamination, HF for native oxide, and the full RCA sequence before epitaxy, oxidation, bonding or metallization. Chosen for your material and the films already on the wafer.

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Piranha (H₂SO₄:H₂O₂)SC-1, SC-2, RCAHF and BOESi, SiC, sapphire, glassPre-bond and pre-epiFrom 1 wafer
2-12 in
Wafer
diameters
4
Standard baths:
piranha, SC-1, SC-2, HF
Per lot
Particle and residue
check as agreed
1
Wafer minimum
order
What each clean does

Four baths, four jobs

Every wet clean is a trade-off between what it removes and what it attacks. The table below is the short version; the review before a lot checks your films and structures against each bath.

01Piranha (H₂SO₄ + H₂O₂)02SC-1 (NH₄OH + H₂O₂)03HF dip (optional)04SC-2 (HCl + H₂O₂)05Rinse and dry

A representative sequence, schematic. The order and the baths used depend on the incoming contamination and the films present; not every wafer needs every step.

CleanChemistryRemovesWatch out for
PiranhaH₂SO₄ : H₂O₂, hotOrganics, resist and polymer residue; leaves a thin chemical oxideAttacks most metals and many polymers; not for wafers with exposed Al, Cu or photoresist structures that must survive
SC-1 (APM)NH₄OH : H₂O₂ : H₂OParticles and light organics by mild oxide etch and lift-offSlow silicon etch and surface roughening if over-processed; not for exposed Al
SC-2 (HPM)HCl : H₂O₂ : H₂OMetallic and ionic contaminationMild; usually follows SC-1
HF or BOEDilute HFNative and chemical oxide; leaves a hydrogen-terminated surfaceRemoves SiO₂ films and undercuts oxide; timing matters
Full RCASC-1, HF, SC-2 in sequenceThe pre-oxidation, pre-epitaxy and pre-bonding standardSequence and HF step selected per surface
At a glance

Piranha, SC-1, SC-2 and RCA Cleaning Services

Scope and specification options. Every figure is confirmed for your program in the quotation.

2-12 in
Wafer diameters
4
Standard baths: piranha, SC-1, SC-2, HF
Per lot
Particle and residue check as agreed
1
Wafer minimum order
Piranha (H₂SO₄:H₂O₂)
SC-1, SC-2, RCA
HF and BOE
Si, SiC, sapphire, glass
Pre-bond and pre-epi
From 1 wafer
Capability

What we clean and how it is checked

ParameterTypicalNote
MaterialsSi, SOI, SiC, sapphire, glass, fused silica, quartz, GaAs and InP with compatible chemistryIII-V and metallized wafers reviewed per bath
Wafer size2 to 12 inch; pieces and couponsCassette or single-wafer handling
Use casesResist and residue removal, pre-epitaxy, pre-oxidation, pre-bonding, pre-metallization, fluorine or organic contamination removalSequence per use case
DryingSpin-rinse dry, IPA or Marangoni per surface and structureReleased MEMS by critical point drying
VerificationParticle count, water contact angle, optical inspection; XPS, TXRF or EDX by agreementCriteria stated in the quotation
TurnaroundShort lots typically within days once receivedConfirmed in the quotation
How a program runs

From incoming wafer to verified surface

Process flow
01Review02Sequence03Clean04Verify05Deliver
  1. 01ReviewMaterial, films present, contamination type, what must survive, downstream step.
  2. 02SequenceBaths, order, times and drying chosen; coupon trial for unusual stacks.
  3. 03CleanWet processing in the agreed sequence with controlled rinse and dry.
  4. 04VerifyInspection per criteria: particles, contact angle, residue; analytics by agreement.
  5. 05DeliverWafers in cleaned cassettes or single-wafer carriers.
Direct answers

Questions engineers ask before ordering

Can you piranha-clean a wafer with metal on it?

Usually no: piranha attacks most metals. We review the exposed films and choose SC-1, solvent or plasma routes where metal must survive.

Do you clean SiC and sapphire?

Yes. Both are chemically robust, so the full RCA and piranha sequences are available; the review concerns the films and the contamination, not the substrate.

What do you need to quote?

Material, size and quantity, the films and structures present, the contamination you want removed, the process that follows, and the cleanliness criterion you need.

Related processes

Processes usually combined with this work

Wafer CleaningSiC ProcessingWafer BondingThin Film DepositionSubstrates
Related service

Wafer Cleaning: the process most often combined with this work, run in the same program.

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Start your project.
Initial response within one business day.

Share your process requirements, substrate, and production volume. A Nanosystems JP Inc. engineer gives an initial response, typically within one business day. A written quotation typically follows within 7-10 business days after we receive the required information and complete any prerequisite NDA.

To speed up technical review, please include:
substrate type & size  ·  target process  ·  quantity  ·  timeline  ·  design files if available (not required for first review)

sales@nanosystemsjp.co.jp · +81-3-5288-5569 · NDA available · All inquiries handled confidentially

Ready to discuss this process?
Initial engineering response typically within one business day. NDA available on request.
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All Services
Full process flow →
Substrates
Substrate & WafersSi, SiC, GaN, glass, sapphire Fused Silica WafersQuartz · borosilicate · low CTE PI Film & SUS Sensor FabRoll-to-roll · sensor patterning
Front-End
Mask FabricationGDS to chrome mask, DRC PhotolithographyE-beam 20nm to 500×600mm NanoimprintingUV & thermal NIL Thin Film DepositionPVD, CVD, ALD, MBE LiftoffMetal pattern · shadow mask ElectroplatingCu TSV fill, DPC, LIGA EtchingICP-RIE, DRIE >50:1 AnnealingN₂/H₂/vacuum/RTA Ion ImplantationB/P/As/Al/N implant CMP & GrindingCu CMP, 50µm thinning DicingBlade, stealth laser Wafer CleaningRCA, plasma, megasonic
Advanced Packaging
Wafer BondingHybrid, eutectic, fusion TSV FabricationHigh AR, void-free Cu fill TSV RevealBackgrind → etch → CMP TGV FabricationThrough-glass via RDL FabricationBCB/PBO/PI + damascene Packaging & AssemblyWire bond, flip-chip 📚 3D/2.5D PackagingTSV+RDL+UBM+C4 AuSn BumpPVD lift-off, fluxless Indium BumpEvap lift-off · cryo/quantum UBM DepositionTi/Pt/Au · adhesion-barrier-Au Gold BumpEvap & plated · Au-Au TC AuGe / AuSi356/363°C eutectic die attach High-Pb Bumps95Pb5Sn · hi-rel C4 SLID / TLPCu/Sn · Au/In · Ag/In Al-Ge Sealing424°C · CMOS-friendly MEMS Ohmic ContactsGaAs · GaN · RTA + TLM Cryo & UHV MetallizationAuSn · Ti/Pd/Au · seal rings Optical AccessWindows · meshes · thru-holes MEMS Vapor CellsDRIE + bond · unfilled bodies Thin-Film-on-InsulatorQuartz-on-Si · LNOI Biochip & MicrofluidicsGlass 500×600mm, NIL SiPho PackagingTSV·RDL·UBM·C4 for PIC
Industries
AI & HPC PackagingCoWoS-style, 2.5D/3D Silicon PhotonicsSOI · AuSn · TSV interposer Quantum TechnologyIon traps · vapor cells · TFOI AutomotiveMEMS sensors, SiC power Life SciencesLab-on-chip, biosensors All Industries → Request a Quote →
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Capabilities Overview
Substrates
Substrate & WafersSi, SiC, GaN, glass, sapphire Fused Silica WafersQuartz · borosilicate · low CTE Glass ProcessingDrilling, etching, polishing PI Film & SUS Sensor FabRoll-to-roll · sensor patterning
Front-End
Mask FabricationGDS to chrome mask, DRC PhotolithographyE-beam 20 nm to 500×600 mm NanoimprintingUV & thermal NIL Thin Film DepositionPVD, CVD, ALD, MBE ALD CoatingConformal oxides, nitrides PECVD DielectricsSiO₂, SiN, SiON, a-Si TFT & BackplaneIGZO · Glass · Display LiftoffMetal pattern · shadow mask ElectroplatingCu TSV fill, DPC, LIGA Electroforming & LIGANi shims, meshes, microstructures EtchingICP-RIE, DRIE >50:1 ICP-RIE EtchingSi, oxide, III-V, SiC, quartz MEMS FoundrySensors, actuators, microfluidics Microchannel CoolingEtched, bonded, heater test chips Thermal Test ChipsHeater dies, multi-zone, RTD Temperature SensorsPt/NiCr RTDs, thermocouples AnnealingN₂ / H₂ / vacuum / RTA Ion ImplantationB / P / As / Al / N implant CMP & GrindingCu CMP, 50 µm thinning Wafer ThinningTo 50 µm on carriers Patterned Test WafersCustom CMP and process evaluation wafers Daisy-Chain Test DiesDummy dies, chains, bump options DicingBlade, stealth laser Stealth & Laser Dicing300 mm Si and glass, SDBG Wafer CleaningRCA, plasma, megasonic Cleaning ChemistryPiranha, SC-1, SC-2, RCA
Advanced Packaging
Wafer BondingHybrid, eutectic, fusion Anodic BondingGlass to silicon, cavities MEMS Cap WafersCavities, ports, seal lands, bonded TSV FabricationHigh AR, void-free Cu fill InterposersSi and glass, TSV/TGV + RDL TSV RevealBackgrind → etch → CMP TGV FabricationThrough-glass via Glass TGV CouponsHole-only to routed prototypes RDL FabricationBCB / PBO / PI + damascene Packaging & AssemblyWire bond, flip-chip Flip-Chip BondingTC, reflow, AuSn, underfill 3D / 2.5D PackagingTSV + RDL + UBM + C4 AuSn BumpPVD lift-off, fluxless Laser SubmountsSi/AlN submounts, optical benches Indium BumpEvap lift-off · cryo/quantum UBM DepositionTi/Pt/Au · adhesion-barrier-Au Cu Pillar & SnAg BumpingPillars with SnAg caps, SnAg bumps Gold BumpEvap & plated · Au-Au TC AuGe / AuSi356/363°C eutectic die attach High-Pb Bumps95Pb5Sn · hi-rel C4 SLID / TLPCu/Sn · Au/In · Ag/In Al-Ge Sealing424°C · CMOS-friendly MEMS Ohmic ContactsGaAs · GaN · RTA + TLM SiC ProcessingContacts, implant, 1800 °C anneal GaN & III-VGaN, GaAs, InP processing Cryo / UHV MetalAuSn · Ti/Pd/Au · rings Optical AccessWindows · meshes · holes Vapor CellsDRIE + bond · unfilled TFOI WafersQuartz-on-Si · LNOI Biochip & MicrofluidicsGlass 500×600 mm, NIL SiPho PackagingTSV · RDL · UBM · C4 for PIC Photonic DevicesSiN/SOI waveguides, gratings
Industries
AI & HPC PackagingCoWoS-style, 2.5D / 3D Silicon PhotonicsSOI · AuSn · TSV interposer AutomotiveMEMS sensors, SiC power Life SciencesLab-on-chip, biosensors All Industries → Request a Quote →