Assembly

Flip-Chip Bonding
and Assembly Services

Die-to-substrate, die-to-wafer and die-to-interposer flip-chip assembly: thermocompression for Cu pillar and Au, reflow for SnAg, AuSn eutectic for photonics and hermetic parts, with alignment, underfill and electrical verification on daisy-chain structures. From single dies to pilot lots, in one program with the bumping that precedes it.

Packaging and assembly →

ThermocompressionReflow (SnAg)AuSn eutecticDie-to-waferUnderfillDaisy-chain check
±2 µm
Placement accuracy
class, reviewed per bonder and part
20 µm
Bump pitch from,
reviewed geometries
1
Die minimum
order
AuSn, SnAg, Cu, Au
Bump
systems
What we assemble

Bonding chosen by the bump, not the other way round

The bump system decides the bonding route: Cu pillar and Au bumps bond by thermocompression, SnAg by reflow, AuSn by eutectic reflow or thermocompression. We quote the assembly together with the bumping so the two are designed as one.

Die (face down)Bumps: AuSn, SnAg, Cu pillar, AuUnderfill (optional)Substrate pads

Schematic, not to scale: a face-down die on its bumps over substrate pads, with optional underfill. Bump system, pitch and stand-off are set by the design; alignment and joint inspection are agreed per program.

01

Thermocompression

Cu pillar with SnAg cap, Au stud and Au bumps, Au-Au and Cu-Cu joints; force, temperature and time per bump system; used for fine pitch and for photonics where flux is excluded.

02

Reflow

SnAg and other solder bumps with flux or fluxless routes; mass reflow after placement for larger pitches and quantities.

03

AuSn eutectic

Fluxless AuSn for lasers, photonics and hermetic assemblies, with the profile set for the stack. See AuSn bumping.

04

Die-to-wafer and interposer

Dies placed on wafers or interposers for 2.5D and 3D stacks, with daisy-chain dies to qualify the joint before product. See test dies.

At a glance

Flip-Chip Bonding and Assembly Services

Scope and specification options. Every figure is confirmed for your program in the quotation.

±2 µm
Placement accuracy class, reviewed per bonder and part
20 µm
Bump pitch from, reviewed geometries
1
Die minimum order
AuSn, SnAg, Cu, Au
Bump systems
Thermocompression
Reflow (SnAg)
AuSn eutectic
Die-to-wafer
Underfill
Daisy-chain check
Capability

Typical ranges

Achievable accuracy and yield depend on bump system, die size, substrate flatness and quantity; the quotation states the values for your parts.

ParameterTypicalNote
Die size0.5 mm to 25 mm edgeThin dies with carrier handling
SubstratesSilicon and glass interposers, ceramic, organic laminates, wafers to 200 mmFlatness reviewed
Bump systemsCu pillar + SnAg, SnAg, AuSn, Au, indiumPitch from 20 µm on reviewed geometries
Placement accuracy±2 µm class with high-accuracy bonders; coarser routes for larger pitchStated per part
ProcessThermocompression, reflow, eutectic; fluxless routes availableAtmosphere per bump system
UnderfillCapillary or no-flow; none for hermetic or photonic parts as requiredMaterial per thermal budget
VerificationDaisy-chain continuity and resistance, X-ray, cross section, shear testAs agreed
How a program runs

From bumped parts to verified assemblies

Process flow
01Define02Bump03Place and bond04Underfill and cure05Verify and deliver
  1. 01DefineDie and substrate, bump system, pitch, accuracy, underfill, verification.
  2. 02BumpBumping and UBM if not already present, on our pages for each system.
  3. 03Place and bondAlignment to marks, thermocompression, reflow or eutectic bonding.
  4. 04Underfill and cureWhere specified; none for hermetic or photonic parts.
  5. 05Verify and deliverDaisy-chain and inspection per agreement; assemblies in trays.
Direct answers

Questions engineers ask before ordering

Can you bump and assemble in one program?

Yes. That is the normal case: the bump system and the bonding route are designed together, and daisy-chain dies qualify the joint before product parts are committed.

Fluxless assembly for photonics?

Yes, by thermocompression or AuSn eutectic routes with no flux, and without underfill where the optical path or hermeticity requires it.

What do you need to quote?

Die and substrate drawings, bump system or pad finish on both sides, pitch and count, accuracy requirement, underfill preference, verification needs, quantity and date.

Related processes

Processes usually combined with this work

Packaging & AssemblyCu Pillar & SnAgAuSn BumpingTest DiesInterposers
Related service

Packaging & Assembly: the process most often combined with this work, run in the same program.

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Start your project.
Initial response within one business day.

Share your process requirements, substrate, and production volume. A Nanosystems JP Inc. engineer gives an initial response, typically within one business day. A written quotation typically follows within 7-10 business days after we receive the required information and complete any prerequisite NDA.

To speed up technical review, please include:
substrate type & size  ·  target process  ·  quantity  ·  timeline  ·  design files if available (not required for first review)

sales@nanosystemsjp.co.jp · +81-3-5288-5569 · NDA available · All inquiries handled confidentially

Ready to discuss this process?
Initial engineering response typically within one business day. NDA available on request.
Request a Quote →
All Services
Full process flow →
Substrates
Substrate & WafersSi, SiC, GaN, glass, sapphire Fused Silica WafersQuartz · borosilicate · low CTE PI Film & SUS Sensor FabRoll-to-roll · sensor patterning
Front-End
Mask FabricationGDS to chrome mask, DRC PhotolithographyE-beam 20nm to 500×600mm NanoimprintingUV & thermal NIL Thin Film DepositionPVD, CVD, ALD, MBE LiftoffMetal pattern · shadow mask ElectroplatingCu TSV fill, DPC, LIGA EtchingICP-RIE, DRIE >50:1 AnnealingN₂/H₂/vacuum/RTA Ion ImplantationB/P/As/Al/N implant CMP & GrindingCu CMP, 50µm thinning DicingBlade, stealth laser Wafer CleaningRCA, plasma, megasonic
Advanced Packaging
Wafer BondingHybrid, eutectic, fusion TSV FabricationHigh AR, void-free Cu fill TSV RevealBackgrind → etch → CMP TGV FabricationThrough-glass via RDL FabricationBCB/PBO/PI + damascene Packaging & AssemblyWire bond, flip-chip 📚 3D/2.5D PackagingTSV+RDL+UBM+C4 AuSn BumpPVD lift-off, fluxless Indium BumpEvap lift-off · cryo/quantum UBM DepositionTi/Pt/Au · adhesion-barrier-Au Gold BumpEvap & plated · Au-Au TC AuGe / AuSi356/363°C eutectic die attach High-Pb Bumps95Pb5Sn · hi-rel C4 SLID / TLPCu/Sn · Au/In · Ag/In Al-Ge Sealing424°C · CMOS-friendly MEMS Ohmic ContactsGaAs · GaN · RTA + TLM Cryo & UHV MetallizationAuSn · Ti/Pd/Au · seal rings Optical AccessWindows · meshes · thru-holes MEMS Vapor CellsDRIE + bond · unfilled bodies Thin-Film-on-InsulatorQuartz-on-Si · LNOI Biochip & MicrofluidicsGlass 500×600mm, NIL SiPho PackagingTSV·RDL·UBM·C4 for PIC
Industries
AI & HPC PackagingCoWoS-style, 2.5D/3D Silicon PhotonicsSOI · AuSn · TSV interposer Quantum TechnologyIon traps · vapor cells · TFOI AutomotiveMEMS sensors, SiC power Life SciencesLab-on-chip, biosensors All Industries → Request a Quote →
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Capabilities Overview
Substrates
Substrate & WafersSi, SiC, GaN, glass, sapphire Fused Silica WafersQuartz · borosilicate · low CTE Glass ProcessingDrilling, etching, polishing PI Film & SUS Sensor FabRoll-to-roll · sensor patterning
Front-End
Mask FabricationGDS to chrome mask, DRC PhotolithographyE-beam 20 nm to 500×600 mm NanoimprintingUV & thermal NIL Thin Film DepositionPVD, CVD, ALD, MBE ALD CoatingConformal oxides, nitrides PECVD DielectricsSiO₂, SiN, SiON, a-Si TFT & BackplaneIGZO · Glass · Display LiftoffMetal pattern · shadow mask ElectroplatingCu TSV fill, DPC, LIGA Electroforming & LIGANi shims, meshes, microstructures EtchingICP-RIE, DRIE >50:1 ICP-RIE EtchingSi, oxide, III-V, SiC, quartz MEMS FoundrySensors, actuators, microfluidics Microchannel CoolingEtched, bonded, heater test chips Thermal Test ChipsHeater dies, multi-zone, RTD Temperature SensorsPt/NiCr RTDs, thermocouples AnnealingN₂ / H₂ / vacuum / RTA Ion ImplantationB / P / As / Al / N implant CMP & GrindingCu CMP, 50 µm thinning Wafer ThinningTo 50 µm on carriers Patterned Test WafersCustom CMP and process evaluation wafers Daisy-Chain Test DiesDummy dies, chains, bump options DicingBlade, stealth laser Stealth & Laser Dicing300 mm Si and glass, SDBG Wafer CleaningRCA, plasma, megasonic Cleaning ChemistryPiranha, SC-1, SC-2, RCA
Advanced Packaging
Wafer BondingHybrid, eutectic, fusion Anodic BondingGlass to silicon, cavities MEMS Cap WafersCavities, ports, seal lands, bonded TSV FabricationHigh AR, void-free Cu fill InterposersSi and glass, TSV/TGV + RDL TSV RevealBackgrind → etch → CMP TGV FabricationThrough-glass via Glass TGV CouponsHole-only to routed prototypes RDL FabricationBCB / PBO / PI + damascene Packaging & AssemblyWire bond, flip-chip Flip-Chip BondingTC, reflow, AuSn, underfill 3D / 2.5D PackagingTSV + RDL + UBM + C4 AuSn BumpPVD lift-off, fluxless Laser SubmountsSi/AlN submounts, optical benches Indium BumpEvap lift-off · cryo/quantum UBM DepositionTi/Pt/Au · adhesion-barrier-Au Cu Pillar & SnAg BumpingPillars with SnAg caps, SnAg bumps Gold BumpEvap & plated · Au-Au TC AuGe / AuSi356/363°C eutectic die attach High-Pb Bumps95Pb5Sn · hi-rel C4 SLID / TLPCu/Sn · Au/In · Ag/In Al-Ge Sealing424°C · CMOS-friendly MEMS Ohmic ContactsGaAs · GaN · RTA + TLM SiC ProcessingContacts, implant, 1800 °C anneal GaN & III-VGaN, GaAs, InP processing Cryo / UHV MetalAuSn · Ti/Pd/Au · rings Optical AccessWindows · meshes · holes Vapor CellsDRIE + bond · unfilled TFOI WafersQuartz-on-Si · LNOI Biochip & MicrofluidicsGlass 500×600 mm, NIL SiPho PackagingTSV · RDL · UBM · C4 for PIC Photonic DevicesSiN/SOI waveguides, gratings
Industries
AI & HPC PackagingCoWoS-style, 2.5D / 3D Silicon PhotonicsSOI · AuSn · TSV interposer AutomotiveMEMS sensors, SiC power Life SciencesLab-on-chip, biosensors All Industries → Request a Quote →