Dicing

Stealth and Laser
Dicing Services

Stealth dicing for silicon and glass up to 300 mm, laser dicing and grooving for brittle and low-k materials, and blade dicing where it is the right tool. For thin wafers, MEMS and photonics dies, glass interposers and SiC, from one wafer, with the process chosen for your material and die size.

All dicing methods →

Stealth dicing (SD)Laser grooving + bladeFull laser dicing300 mm siliconGlass and fused silicaSDBG for thin dies
300 mm
Silicon and glass
wafer diameter to
~0 µm
Kerf loss with
stealth dicing
50 µm
Wafer thickness
from, on carrier or frame
1
Wafer minimum
order
Methods

Three laser routes and when each one wins

Stealth dicing focuses a laser inside the wafer and separates dies by tape expansion: no kerf loss, no water, no chipping on the front side. Laser grooving opens a channel through metal or low-k layers before a blade finishes the cut. Full laser dicing ablates through thin or brittle material where a blade would chip it.

Laser focused inside the waferModified layer (SD layer)Tape expansion separates diesNo kerf loss, dry process

Schematic, not to scale: the laser is focused below the surface to form a modified layer; the frame tape is expanded to separate the dies. Layer count and expansion are set for the material and thickness.

01

Stealth dicing

Silicon and glass wafers to 300 mm, thin wafers on frame, MEMS with released structures and photonic dies where a wet blade cut is not acceptable.

02

Laser grooving plus blade

Wafers with test structures, metal or low-k in the streets; the groove removes the delaminating layers and the blade cuts the silicon cleanly.

03

Full laser dicing

Glass, fused silica, sapphire, SiC and very thin wafers where chipping and cracking would follow a blade; profile and edge quality reviewed per material.

04

SDBG for thin dies

Stealth dicing before grinding: the modified layer is formed first, the wafer is thinned on a carrier, and the dies separate at the target thickness without handling a thin wafer through a saw.

At a glance

Stealth and Laser Dicing Services

Scope and specification options. Every figure is confirmed for your program in the quotation.

300 mm
Silicon and glass wafer diameter to
~0 µm
Kerf loss with stealth dicing
50 µm
Wafer thickness from, on carrier or frame
1
Wafer minimum order
Stealth dicing (SD)
Laser grooving + blade
Full laser dicing
300 mm silicon
Glass and fused silica
SDBG for thin dies
Capability

Typical ranges

Values are typical process windows; edge quality, die strength and chipping criteria are agreed per program.

ParameterTypicalNote
Wafer diameter2 to 12 inch (50 to 300 mm), pieces and panelsFrame and tape per diameter
MaterialsSi, SOI, glass, fused silica, quartz, sapphire, SiC, GaAs, InPLaser parameters per material
Thickness50 µm to 1 mm; SDBG to 50 µmCarrier or frame support below ~200 µm
Die sizeFrom about 0.3 mm; any rectangle, plus non-rectangular by laserStreet width per method, from ~20 µm for stealth
KerfNear zero for stealth; laser groove and blade per recipeMeasured on request
Front sideStealth and laser keep the front dry; bumped and patterned wafers reviewedProtective film where needed
DeliveryOn frame or tape, in trays or gel packs, sorted by mapInspection per agreed criteria
How a program runs

From wafer to sorted dies

Process flow
01Review02Recipe03Mount and dice04Separate05Inspect and deliver
  1. 01ReviewMaterial, thickness, streets, die size, front-side condition, target edge quality.
  2. 02RecipeMethod chosen and, for a new material, a coupon trial with edge inspection.
  3. 03Mount and diceFrame mounting, stealth or laser processing, blade where specified.
  4. 04SeparateTape expansion or blade finish; thinning first for SDBG flows.
  5. 05Inspect and deliverChipping and edge check per criteria; trays, gel packs or frame with a map.
Direct answers

Questions engineers ask before ordering

Can you dice 300 mm glass wafers?

Yes, by stealth or laser routes, with the process set for the glass type and thickness; edge quality is reviewed on a coupon before the lot.

Can you dice a wafer that already has bumps?

Yes. Stealth and laser routes keep the front dry; bumped and patterned front sides are reviewed for protection and for the street layout.

What do you need to quote?

Wafer material, diameter and thickness, die size and street width, front-side condition, delivery format, quantity and date. A wafer map or GDS helps but is not required for the first answer.

Related processes

Processes usually combined with this work

Wafer DicingWafer ThinningGlass ProcessingSiC ProcessingTest Dies
Related service

Wafer Dicing: the process most often combined with this work, run in the same program.

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Start your project.
Initial response within one business day.

Share your process requirements, substrate, and production volume. A Nanosystems JP Inc. engineer gives an initial response, typically within one business day. A written quotation typically follows within 7-10 business days after we receive the required information and complete any prerequisite NDA.

To speed up technical review, please include:
substrate type & size  ·  target process  ·  quantity  ·  timeline  ·  design files if available (not required for first review)

sales@nanosystemsjp.co.jp · +81-3-5288-5569 · NDA available · All inquiries handled confidentially

Ready to discuss this process?
Initial engineering response typically within one business day. NDA available on request.
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All Services
Full process flow →
Substrates
Substrate & WafersSi, SiC, GaN, glass, sapphire Fused Silica WafersQuartz · borosilicate · low CTE PI Film & SUS Sensor FabRoll-to-roll · sensor patterning
Front-End
Mask FabricationGDS to chrome mask, DRC PhotolithographyE-beam 20nm to 500×600mm NanoimprintingUV & thermal NIL Thin Film DepositionPVD, CVD, ALD, MBE LiftoffMetal pattern · shadow mask ElectroplatingCu TSV fill, DPC, LIGA EtchingICP-RIE, DRIE >50:1 AnnealingN₂/H₂/vacuum/RTA Ion ImplantationB/P/As/Al/N implant CMP & GrindingCu CMP, 50µm thinning DicingBlade, stealth laser Wafer CleaningRCA, plasma, megasonic
Advanced Packaging
Wafer BondingHybrid, eutectic, fusion TSV FabricationHigh AR, void-free Cu fill TSV RevealBackgrind → etch → CMP TGV FabricationThrough-glass via RDL FabricationBCB/PBO/PI + damascene Packaging & AssemblyWire bond, flip-chip 📚 3D/2.5D PackagingTSV+RDL+UBM+C4 AuSn BumpPVD lift-off, fluxless Indium BumpEvap lift-off · cryo/quantum UBM DepositionTi/Pt/Au · adhesion-barrier-Au Gold BumpEvap & plated · Au-Au TC AuGe / AuSi356/363°C eutectic die attach High-Pb Bumps95Pb5Sn · hi-rel C4 SLID / TLPCu/Sn · Au/In · Ag/In Al-Ge Sealing424°C · CMOS-friendly MEMS Ohmic ContactsGaAs · GaN · RTA + TLM Cryo & UHV MetallizationAuSn · Ti/Pd/Au · seal rings Optical AccessWindows · meshes · thru-holes MEMS Vapor CellsDRIE + bond · unfilled bodies Thin-Film-on-InsulatorQuartz-on-Si · LNOI Biochip & MicrofluidicsGlass 500×600mm, NIL SiPho PackagingTSV·RDL·UBM·C4 for PIC
Industries
AI & HPC PackagingCoWoS-style, 2.5D/3D Silicon PhotonicsSOI · AuSn · TSV interposer Quantum TechnologyIon traps · vapor cells · TFOI AutomotiveMEMS sensors, SiC power Life SciencesLab-on-chip, biosensors All Industries → Request a Quote →
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Capabilities Overview
Substrates
Substrate & WafersSi, SiC, GaN, glass, sapphire Fused Silica WafersQuartz · borosilicate · low CTE Glass ProcessingDrilling, etching, polishing PI Film & SUS Sensor FabRoll-to-roll · sensor patterning
Front-End
Mask FabricationGDS to chrome mask, DRC PhotolithographyE-beam 20 nm to 500×600 mm NanoimprintingUV & thermal NIL Thin Film DepositionPVD, CVD, ALD, MBE ALD CoatingConformal oxides, nitrides PECVD DielectricsSiO₂, SiN, SiON, a-Si TFT & BackplaneIGZO · Glass · Display LiftoffMetal pattern · shadow mask ElectroplatingCu TSV fill, DPC, LIGA Electroforming & LIGANi shims, meshes, microstructures EtchingICP-RIE, DRIE >50:1 ICP-RIE EtchingSi, oxide, III-V, SiC, quartz MEMS FoundrySensors, actuators, microfluidics Microchannel CoolingEtched, bonded, heater test chips Thermal Test ChipsHeater dies, multi-zone, RTD Temperature SensorsPt/NiCr RTDs, thermocouples AnnealingN₂ / H₂ / vacuum / RTA Ion ImplantationB / P / As / Al / N implant CMP & GrindingCu CMP, 50 µm thinning Wafer ThinningTo 50 µm on carriers Patterned Test WafersCustom CMP and process evaluation wafers Daisy-Chain Test DiesDummy dies, chains, bump options DicingBlade, stealth laser Stealth & Laser Dicing300 mm Si and glass, SDBG Wafer CleaningRCA, plasma, megasonic Cleaning ChemistryPiranha, SC-1, SC-2, RCA
Advanced Packaging
Wafer BondingHybrid, eutectic, fusion Anodic BondingGlass to silicon, cavities MEMS Cap WafersCavities, ports, seal lands, bonded TSV FabricationHigh AR, void-free Cu fill InterposersSi and glass, TSV/TGV + RDL TSV RevealBackgrind → etch → CMP TGV FabricationThrough-glass via Glass TGV CouponsHole-only to routed prototypes RDL FabricationBCB / PBO / PI + damascene Packaging & AssemblyWire bond, flip-chip Flip-Chip BondingTC, reflow, AuSn, underfill 3D / 2.5D PackagingTSV + RDL + UBM + C4 AuSn BumpPVD lift-off, fluxless Laser SubmountsSi/AlN submounts, optical benches Indium BumpEvap lift-off · cryo/quantum UBM DepositionTi/Pt/Au · adhesion-barrier-Au Cu Pillar & SnAg BumpingPillars with SnAg caps, SnAg bumps Gold BumpEvap & plated · Au-Au TC AuGe / AuSi356/363°C eutectic die attach High-Pb Bumps95Pb5Sn · hi-rel C4 SLID / TLPCu/Sn · Au/In · Ag/In Al-Ge Sealing424°C · CMOS-friendly MEMS Ohmic ContactsGaAs · GaN · RTA + TLM SiC ProcessingContacts, implant, 1800 °C anneal GaN & III-VGaN, GaAs, InP processing Cryo / UHV MetalAuSn · Ti/Pd/Au · rings Optical AccessWindows · meshes · holes Vapor CellsDRIE + bond · unfilled TFOI WafersQuartz-on-Si · LNOI Biochip & MicrofluidicsGlass 500×600 mm, NIL SiPho PackagingTSV · RDL · UBM · C4 for PIC Photonic DevicesSiN/SOI waveguides, gratings
Industries
AI & HPC PackagingCoWoS-style, 2.5D / 3D Silicon PhotonicsSOI · AuSn · TSV interposer AutomotiveMEMS sensors, SiC power Life SciencesLab-on-chip, biosensors All Industries → Request a Quote →